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ADVANCE INFORMATION
MICRONAS
VDP 313xY Video Processor Family
Edition August 15, 2000 6251-519-1AI
MICRONAS
VDP 313xY
Contents Page 5 5 5 6 7 7 7 7 7 7 7 7 8 9 9 10 10 10 10 10 11 11 12 12 13 13 13 14 14 15 15 15 16 17 17 17 18 18 18 18 19 19 19 21 21 22 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.3. 2.4. 2.4.1. 2.4.2. 2.4.3. 2.4.4. 2.4.5. 2.4.6. 2.4.7. 2.4.8. 2.4.9. 2.4.10. 2.5. 2.6. 2.7. 2.8. 2.9. 2.10. 2.10.1. 2.10.2. 2.10.3. 2.10.4. 2.10.5. 2.10.6. 2.10.7. 2.10.8. 2.10.9. 2.10.10. 2.10.11. 2.10.12. 2.10.13. 2.11. 2.11.1. 2.11.2. Title Introduction Features System Architecture Video Processor Family Functional Description Introduction Video Front End Input Selection Clamping Automatic Gain Control Analog-to-Digital Converters Digitally Controlled Clock Oscillator Adaptive Comb Filter Color Decoder IF-Compensation Demodulator Chrominance Filter Frequency Demodulator Burst Detection / Saturation Control Color Killer Operation Automatic standard recognition PAL Compensation/1-H Comb Filter Luminance Notch Filter Skew Filtering Horizontal Scaler Blackline Detector Test Pattern Generator Video Sync Processing Macrovision detection Display Part Luminance Contrast Adjustment Black Level Expander Dynamic Peaking Digital Brightness Adjustment Soft Limiter Chrominance Interpolation Chrominance Transient Improvement Inverse Matrix RGB Processing Picture Frame Generator Priority Decoder Scan Velocity Modulation Display Phase Shifter Video Back End CRT Measurement and Control SCART Output Signal
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Contents, continued Page 23 23 24 24 24 26 26 27 27 27 28 28 28 29 29 30 48 51 52 52 52 55 56 57 59 59 59 60 61 62 62 62 62 63 64 64 66 66 66 66 67 67 67 67 67 68 Section 2.11.3. 2.11.4. 2.11.5. 2.11.6. 2.11.7. 2.12. 2.12.1. 2.12.2. 2.12.3. 2.12.4. 2.12.5. 2.12.6. 2.13. 2.14. 2.14.1. 2.14.2. 2.14.2.1. 2.14.2.2. 3. 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.6.1. 3.6.2. 3.6.2.1. 3.6.3. 3.6.4. 3.6.4.1. 3.6.4.2. 3.6.4.3. 3.6.4.4. 3.6.4.5. 3.6.4.6. 3.6.4.7. 3.6.4.8. 3.6.4.9. 3.6.4.10. 3.6.4.11. 3.6.4.12. 3.6.4.13. 3.6.4.14. 3.6.4.15. 3.6.4.16. Title Average Beam Current Limiter Analog RGB Insertion Fast Blank Monitor Half Contrast Control IO Port Expander Synchronization and Deflection Deflection Processing Angle & Bow Correction Horizontal Phase Adjustment Vertical and East/West Deflection EHT Compensation Protection Circuitry Reset and Power On Serial Interface I2C-Bus Interface Control and Status Registers Scaler Adjustment Calculation of Vertical and East-West Deflection Coefficients Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Analog Input and Output Recommendations Recommended Crystal Characteristics Characteristics General Characteristics I2C Bus Interface Reset Input Power-up Sequence Test Input Analog Video Front-End and A/D Converters Horizontal Flyback Input Horizontal Drive Output Vertical Protection Input Vertical Safety Input Vertical and East/West D/A Converter Output Combined Sync, Vertical Sync, Interlace and Front Sync Output CLK20 Output Sense A/D Converter Input Range Switch Output Scan Velocity Modulation Output
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Contents, continued Page 68 69 70 70 73 74 76 Section 3.6.4.17. 3.6.4.18. 3.6.4.19. 3.6.4.20. 3.6.4.21. 4. 5. Title D/A Converter Reference Analog RGB and FB Inputs Half Contrast Switch Input Analog RGB Outputs, D/A Converters IO Ports Application Circuit Data Sheet History
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- black-level expander - dynamic peaking - soft limiter (gamma correction)
Video Processor Family 1. Introduction The VDP 313xY is a video IC family of high-quality single-chip video processors. Modular design and a submicron technology allow the economic integration of features in all classes of TV sets. The VDP 313xY family is based on the VDP 31xxB including YCRCB inputs for DVD component signals. The main features of the VDP 3130Y are
- color transient improvement RGB Processing and Deflection - programmable RGB matrix - two analog RGB / Fastblank inputs - half-contrast switch - picture frame generator
1.1. Features Video Decoding and Processing - four CVBS, one S-VHS input, one YCRCB component input - integrated high-quality A/D converters and associated clamp and AGC circuits - adaptive 2H comb filter Y/C separator - multistandard color decoder PAL/NTSC/SECAM including all substandards - multistandard sync decoder - automatic standard recognition - black-line detector - linear horizontal scaling (0.25...4), as well as nonlinear horizontal scaling "Panoramavision"
- scan velocity modulation output - high-performance H/V deflection - separate ADC for tube measurements - EHT compensation - angle and bow correction - one 20.25 MHz crystal, few external components - I2C-Bus Interface - 64-pin PSDIP package
1.2. System Architecture Fig. 1-1 shows the block diagram of the video processor
SVM CIN1 CIN2/CRIN CBIN VIN1 VIN2 VIN3 VIN4 VOUT 2H Adaptive Combfilter RGB/FB IN1 RGB/FB IN2 Half Contrast RGB OUT
Analog Frontend AGC, 2x8 bit ADC
Color Decoder NTSC, PAL, SECAM
Horizontal Scaler Panorama Mode
Display Processor RGB Matrix, CLUT, Scan Veloc.
Analog Backend 3x10 bit DAC, Tube Control, RGB Switch
20.25 MHz
Clock Gen. DCO
I2C
Sync and Deflection
Measurement ADC
I2C
H/V/EW
Sense
Fig. 1-1: Block diagram of the VDP 313xY
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1.3. Video Processor Family Each member of the family contains the entire video, display, and deflection processing for 4:3 and 16:9, 50/ 60 Hz TV sets. Its performance and flexibility allow the user to standardize his product development. Hardware and software applications can profit from the modularity, as well as manufacturing, systems support or maintenance. An overview of the VDP 313xY video processor family is shown in Fig. 1-2.
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The new VDP 313xY family is the next generation of Video and Deflection Processors. The main differences towards the VDP 31xxB family are - YCRCB component input - angle and bow correction - automatic standard recognition - detection of Macrovision signals - no dig. RGB interface for TPU 3050 - no stand-by input mode and CLK5 output - minor changes of pinout
Color Trans. Impr.
2H adapt. Comb
Scan Vel. Mod.
Prog. RGB Matrix
Horizontal Scaler
1H Combfilter
RGB Insertion
VDP 313xY Family VDP 3134Y VDP 3133Y VDP 3132Y VDP 3131Y VDP 3130Y

Fig. 1-2: VDP 313xY family overview
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Tube Control
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rent sources. The clamping level is the back porch of the video signal. S-VHS chrominance is also AC coupled. The input pin is internally biased to the center of the ADC input range. The chrominance inputs for YCRCB need to be AC coupled using clamping capacitors. It is strongly recommended to use 5 MHz anti-alias low-pass filters on each input. Each channel is sampled at 10.125 MHz with a resolution of 8 bit and a clamping level of 128.
2. Functional Description 2.1. Introduction The VDP 313xY includes complete video, display and deflection processing. All processing is done digitally, the video frontend and video backend are interfacing to the analog world. Most functions of the VDP can be controlled by software via I2C-Bus interface (see Section 2.14.1. on page 29).
2.2. Video Front End This block provides the analog interfaces to all video inputs and mainly carries out analog-to-digital conversion for the following digital video processing. A block diagram is given in Fig. 2-1. Most of the functional blocks in the front-end are digitally controlled (clamping, AGC, and clock-DCO). The control loops are closed by the Fast Processor (FP) embedded in the video decoder. 2.2.3. Automatic Gain Control A digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/-4.5 dB in 64 logarithmic steps to the optimal range of the ADC. The gain of the video input stage including the ADC is 213 steps/V with the AGC set to 0 dB. The gain of the chrominance path in the YCRCB mode is fix and adapted to a nominal amplitude of 0.7 Vpp. However, if an overflow of the ADC occurs an extended signal range of 1 Vpp can be selected. 2.2.4. Analog-to-Digital Converters Two ADCs are provided to digitize the input signals. Each converter runs with 20.25 MHz and has 8 bit resolution. An integrated bandgap circuit generates the required reference voltages for the converters. The two ADCs are of a 2-stage subranging type.
2.2.1. Input Selection Up to seven analog inputs can be connected. Four inputs are for input of composite video or S-VHS luminance signal. These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. Two inputs are for connection of S-VHS carrier-chrominance signal. These inputs are internally biased and have a fixed gain amplifier. For analog YCRCB signals (e.g. from DVD players) the selected luminance input is used together with CBIN and CRIN.
2.2.5. Digitally Controlled Clock Oscillator 2.2.2. Clamping The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the coupling capacitors and is generated by digitally controlled curCVBS/Y CVBS/Y CVBS/Y CVBS/Y Chroma Chroma VIN1 VIN2 VIN3 VIN4 CIN1 CIN2 CRIN input mux clamp
AGC +6/-4.5 dB
The clock generation is also a part of the analog front end. The crystal oscillator is controlled digitally by the control processor. The clock frequency can be adjusted within 150 ppm.
ADC
digital CVBS or Luma
gain bias ADC digital Chroma system clocks reference generation DVCO 150 ppm frequency
Chroma
CBIN
clamp
mux
20.25 MHz Fig. 2-1: Video front-end
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2.3. Adaptive Comb Filter The adaptive comb filter is used for high-quality luminance/chrominance separation for PAL or NTSC signals. The comb filter improves the luminance resolution (bandwidth) and reduces interferences like cross-luminance and cross-color artifacts. The adaptive algorithm can eliminate most of the mentioned errors without introducing new artifacts or noise. A block diagram of the comb filter is shown in Fig. 2-1. The filter uses two line delays to process the information of three adjacent video lines. To have a fixed phase relationship of the color subcarrier in the three channels, the system clock (20.25 MHz) is fractionally locked to the color subcarrier. This allows the processing of all color standards and substandards using a single crystal frequency. The CVBS signal in the three channels is filtered at the subcarrier frequency by a set of bandpass/notch filters. The output of the three channels is used by the adaption logic to select the weighting that is used to reconstruct the luminance/chrominance signal from the 4 bandpass/notch filter signals. By using soft mixing of the 4 signals switching artifacts of the adaption algorithm are completely suppressed. The comb filter uses the middle line as reference, therefore, the comb filter delay is one line. If the comb filter is switched off, the delay lines are used to pass the luminance/ chrominance signals from the A/D converters to the luminance/ chrominance outputs. Thus, the comb filter delay is always one line. Various parameters of the comb filter are adjustable, hence giving to the user the ability to adjust his own desired picture quality.
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Two parameters (KY, KC) set the global gain of luminance and chrominance comb separately; these values directly weigh the adaption algorithm output. In this way, it is possible to obtain a luminance/chrominance separation ranging from standard notch/bandpass to full comb decoding. The parameter KB allows to choose between the two proposed comb booster modes. This so-called feature widely improves vertical high to low frequency transitions areas, the typical example being a multiburst to dc change. For KB = 0, this improvement is kept moderate, whereas, in case of KB = 1, it is maximum, but the risk to increase the "hanging dots" amount for some given color transitions is higher. Using the default setting, the comb filter has separate luminance and chrominance decision algorithms; it is however possible to switch the chrominance comb factor to the current luminance adaption output by setting CC to 1. Another interesting feature is the programmable limitation of the luminance comb amount; proper limitation, associated to adequate luminance peaking, gives rise to an enhanced 2-D resolution homogeneity. This limitation is set by the parameter CLIM, ranging from 0 (no limitation) to 31 (max. limitation). The DAA parameter (1:off, 0:on) is used to disable/ enable a very efficient built-in "rain effect" suppressor; many comb filters show this side effect which gives some vertical correlation to a 2-D uniform random area, due to the vertical filtering. This unnatural-looking phenomenon is mostly visible on tuner images, since they are always corrupted by some noise; and this looks like rain.
CVBS Input 1H Delay Line Bandpass/ Notch Filter Bandpass Filter
Luma / Chroma Mixers Adaption Logic
Bandpass Filter
Luma Output
Chroma Output
1H Delay Line Chroma Input
Fig. 2-1: Block diagram of the adaptive comb filter (PAL mode)
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2.4.1. IF-Compensation With off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color subcarrier is compensated. Four different settings of the IF-compensation are possible: - flat (no compensation) - 6 dB/octave - 12 dB/octave - 10 dB/MHz The last setting gives a very large boost to high frequencies. It is provided for SECAM signals that are decoded using a SAW filter specified originally for the PAL standard.
2.4. Color Decoder In this block, the standard luminance/chrominance (luma/chroma) separation and multistandard color demodulation is carried out. The color demodulation uses an asynchronous clock, thus allowing a unified architecture for all color standards. A block diagram of the color decoder is shown in Fig. 2-3. The luminance as well as the chrominance processing, is shown here. The color decoder provides also some special modes, e.g. wide band chrominance format which is intended for S-VHS wide bandwidth chrominance. If the adaptive comb filter is used for luminance/ chrominance separation, the color decoder uses the S-VHS mode processing. The output of the color decoder is YCRCB in a 4:2:2 format.
Fig. 2-2: Frequency response of chrominance IF-compensation
Luma / CVBS
Notch Filter
Luma
MUX
1 H Delay
CrossSwitch
Chroma
ACC MUX IF Compensation DC-Reject Mixer Lowpass Filter Phase/Freq Demodulator
Chroma
ColorPLL/ColorACC Fig. 2-3: Color decoder
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2.4.2. Demodulator The entire signal (which might still contain luminance) is now quadrature-mixed to the baseband. The mixing frequency is equal to the subcarrier for PAL and NTSC, thus achieving the chrominance demodulation. For SECAM, the mixing frequency is 4.286 MHz giving the quadrature baseband components of the FM modulated chrominance. After the mixer, a lowpass filter selects the chrominance components; a downsampling stage converts the color difference signals to a multiplexed half rate data stream. The subcarrier frequency in the demodulator is generated by direct digital synthesis; therefore, substandards such as PAL 3.58 or NTSC 4.43 can also be demodulated.
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2.4.4. Frequency Demodulator The frequency demodulator for demodulating the SECAM signal is implemented as a CORDIC-structure. It calculates the phase and magnitude of the quadrature components by coordinate rotation. The phase output of the CORDIC processor is differentiated to obtain the demodulated frequency. After the deemphasis filter, the Dr and Db signals are scaled to standard CRCB amplitudes and fed to the crossover-switch.
2.4.5. Burst Detection / Saturation Control In the PAL/NTSC-system the burst is the reference for the color signal. The phase and magnitude outputs of the CORDIC are gated with the color key and used for controlling the phase-lock-loop (APC) of the demodulator and the automatic color control (ACC) in PAL/ NTSC. The ACC has a control range of +30...-6 dB. Color saturation can be selected once for all color standards. In PAL/NTSC it is used as reference for the ACC. In SECAM the necessary gains are calculated automatically. For SECAM decoding, the frequency of the burst is measured. Thus, the current chrominance carrier frequency can be identified and is used to control the SECAM processing. The burst measurements also control the color killer operation; they are used for automatic standard detection as well.
2.4.3. Chrominance Filter The demodulation is followed by a lowpass filter for the color difference signals for PAL/NTSC. SECAM requires a modified lowpass function with bell-filter characteristic. At the output of the lowpass filter, all luminance information is eliminated. The lowpass filters are calculated in time multiplex for the two color signals. Three bandwidth settings (narrow, normal, broad) are available for each standard. For PAL/NTSC, a wide band chrominance filter can be selected. This filter is intended for high bandwidth chrominance signals, e.g. a nonstandard wide bandwidth S-VHS signal.
2.4.6. Color Killer Operation The color killer uses the burst-phase/burst-frequency measurement to identify a PAL/NTSC or SECAM color signal. For PAL/NTSC, the color is switched off (killed) as long as the color subcarrier PLL is not locked. For SECAM, the killer is controlled by the toggle of the burst frequency. The burst amplitude measurement is used to switch-off the color if the burst amplitude is below a programmable threshold. Thus, color will be killed for very noisy signals. The color amplitude killer has a programmable hysteresis.
PAL/NTSC
SECAM
Fig. 2-4: Frequency response of chrominance filters
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2.4.8. PAL Compensation/1-H Comb Filter The color decoder uses one fully integrated delay line. Only active video is stored. The delay line application depends on the color standard: - NTSC: - PAL: 1-H comb filter or color compensation color compensation
2.4.7. Automatic standard recognition The burst-frequency measurement is also used for automatic standard recognition (together with the status of horizontal and vertical locking) thus allowing a completely independent search of the line and color standard of the input signal. The following standards can be distinguished: - PAL B,G,H,I - NTSC M - SECAM - NTSC 44 - PAL M - PAL N - PAL 60 For a preselection of allowed standards, the recognition can be enabled/disabled via I2C bus for each standard separately. If at least one standard is enabled, the VDP 313xY checks regularly the horizontal and vertical locking of the input signal and the state of the color killer. If an error exists for several adjacent fields a new standard search is started. Depending on the measured line number and burst frequency the current standard is selected.
- SECAM: crossover-switch In the NTSC compensated mode, Fig. 2-5 c), the color signal is averaged for two adjacent lines. Thus, cross-color distortion and chrominance noise is reduced. In the NTSC combfilter mode, Fig. 2-5 d), the delay line is in the composite signal path, thus allowing reduction of cross-color components, as well as cross-luminance. The loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information. If the 2-H adaptive comb filter is used, then the 1-H NTSC comb filter should not be used.
CVBS For error handling the recognition algorithm delivers the following status information: - search active (busy) - search terminated, but failed - found standard is disabled - vertical standard invalid - no color found - standard switched
8
Notch filter Chroma Process.
Y
Luma
8
Y
Chroma Process.
chroma CR CB
8
CRCB
a) conventional CVBS
8 Notch filter
b) S-VHS Y
Chroma Process.
1H Delay
CR CB
c) compensated CVBS
8 Notch filter
Y
1H Delay
Chroma Process.
CR CB
d) comb filter Fig. 2-5: NTSC color decoding options
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2.4.9. Luminance Notch Filter CVBS
8 Notch filter Chroma Process. 1H Delay
Y
CR C B
a) conventional Luma
8
Y
Chroma Process. 1H Delay
If a composite video signal is applied, the color information is suppressed by a programmable notch filter. The position of the filter center frequency depends on the subcarrier frequency for PAL/NTSC. For SECAM, the notch is directly controlled by the chrominance carrier frequency. This considerably reduces the cross-luminance. The frequency responses for all three systems are shown in Fig. 2-8.
Chroma
8
CR CB
10 0
dB
b) S-VHS Fig. 2-6: PAL color decoding options
-10
-20
-30
CVBS
8
Notch filter Chroma Process. 1H Delay MUX
Y
-40 0 2 4 6 8 10
MHz
PAL/NTSC notch filter CR C B
10 dB
Fig. 2-7: SECAM color decoding
0 -10
-20
-30
-40 0 2 4 6 8 10
MHz
SECAM notch filter Fig. 2-8: Frequency responses of the luminance notch filter for PAL, NTSC, SECAM
2.4.10.Skew Filtering The system clock is free-running and not locked to the TV line frequency. Therefore, the ADC sampling pattern is not orthogonal. The decoded YCRCB signals are converted to an orthogonal sampling raster by the skew filters, which are part of the scaler block. The skew filters allow the application of a group delay to the input signals without introducing waveform or frequency response distortion. The amount of phase shift of this filter is controlled by the horizontal PLL1. The accuracy of the filters is 1/32 clocks for luminance and 1/4 clocks for chrominance. Thus the 4:2:2 YCRCB data is in an orthogonal pixel format even in the case of nonstandard input signals such as VCR.
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2.6. Blackline Detector In case of a letterbox format input video, e.g. Cinemascope, PAL+ etc., black areas at the upper and lower part of the picture are visible. It is suitable to remove or reduce these areas by a vertical zoom and/or shift operation. The VDP 313xY supports this feature by a letterbox detector. The circuitry detects black video lines by measuring the signal amplitude during active video. For every field the number of black lines at the upper and lower part of the picture are measured, compared to the previous measurement and the minima are stored in the I2C-register BLKLIN. To adjust the picture amplitude, the external controller reads this register, calculates the vertical scaling coefficient and transfers the new settings, e.g. vertical sawtooth parameters, horizontal scaling coefficient etc., to the VDP 313xY. Letterbox signals containing logos on the left or right side of the black areas are processed as black lines, while subtitles, inserted in the black areas, are processed as non-black lines. Therefore the subtitles are visible on the screen. To suppress the subtitles, the vertical zoom coefficient is calculated by selecting the larger number of black lines only. Dark video scenes with a low contrast level compared to the letterbox area are indicated by the BLKPIC bit.
2.5. Horizontal Scaler The 4:2:2 YCRCB signal from the color decoder is processed by the horizontal scaler. The scaler block allows a linear or nonlinear horizontal scaling of the input video signal in the range of 0.25 to 4. Nonlinear scaling, also called panorama vision, provides a geometrical distortion of the input picture. It is used to fit a picture with 4:3 format on a 16:9 screen by stretching the picture geometry at the borders. Also, the inverse effect can be produced by the scaler. A summary of scaler modes is given in Table 2-1. The scaler contains a programmable decimation filter, a 1-line FIFO memory, and a programmable interpolation filter. The scaler input filter is also used for pixel skew correction (see Section 2.4.10. on page 12). The decimator/interpolator structure allows optimal use of the FIFO memory. The controlling of the scaler is done by the internal Fast Processor.
Table 2-1: Scaler modes 2.7. Test Pattern Generator Mode Compression 4:3 16:9 Panorama 4:3 16:9 Zoom 4:3 4:3 Scale Factor 0.75 linear nonlinear compr 1.33 linear Description 4:3 source displayed on a 16:9 tube, with side panels 4:3 source displayed on a 16:9 tube, Borders distorted Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan with cropping of side panels Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan, borders distorted, no cropping The YCRCB outputs can be switched to a test mode where YCRCB data are generated digitally in the VDP 313xY. Test patterns include luminance/chrominance ramps and flat fields.
Panorama 4:3 4:3
nonlinear zoom
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2.8. Video Sync Processing Fig. 2-9 shows a block diagram of the front-end sync processing. To extract the sync information from the video signal, a linear phase lowpass filter eliminates all noise and video contents above 1 MHz. The sync is separated by a slicer; the sync phase is measured. A variable window can be selected to improve the noise immunity of the slicer. The phase comparator measures the falling edge of sync, as well as the integrated sync pulse. The sync phase error is filtered by a phase-locked loop that is computed by the FP. All timing in the front-end is derived from a counter that is part of this PLL, and it thus counts synchronously to the video signal. A separate hardware block measures the signal back porch and also allows gathering the maximum/minimum of the video signal. This information is processed by the FP and used for gain control and clamping.
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For vertical sync separation, the sliced video signal is integrated. The FP uses the integrator value to derive vertical sync and field information. The information extracted by the video sync processing is multiplexed onto the hardware front sync signal (FSY) and is distributed to the rest of the video processing system. The data for the vertical deflection, the sawtooth, and the East-West correction signal is calculated by the VDP 313xY. The data is buffered in a FIFO and transferred to the back-end by a single wire interface. Frequency and phase characteristics of the analog video signal are derived from PLL1. The results are fed to the scaler unit for data interpolation and orthogonalization and to the clock synthesizer for line-locked clock generation. Horizontal and vertical syncs are latched with the line-locked clock.
PLL1 lowpass 1 MHz & syncslicer video input clamp & signal meas. horizontal sync separation phase comparator counter & lowpass
frontend timing
front sync generator
front sync skew vblank field clock H/V syncs
clock synthesizer syncs
clamping, colorkey, FIFO_write Sawtooth Parabola Calculation vertical serial data vertical E/W sawtooth
vertical sync separation Fig. 2-9: Sync separation block diagram
FIFO
2.9. Macrovision detection Video signals from Macrovision encoded VCR tapes are decoded without loss of picture quality. However, it might be necessary in some applications to detect the presence of Macrovision encoded video signals. This is possible by reading the Macrovision status register (MCV_STATUS). Macrovision encoded video signals typically have AGC pulses and pseudo sync pulses added during VBI. The amplitude of the AGC pulses is modulated in time. The Macrovision detection logic measures the VBI lines and compares the signal against thresholds.
The window in which the video lines are checked for Macrovision pulses can be defined in terms of start and stop line (e.g. 6-15 for NTSC).
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the picture are changed to black, while bright areas remain unchanged. The advantage of this black level expander is that the black expansion is performed only if it will be most noticeable to the viewer. The black level expander works adaptively. Depending on the measured amplitudes Lmin and Lmax of the lowpass-filtered luminance (during a programmalbe vertical window) and an adjustable coefficient BTLT, a tilt point Lt is established by Lt = Lmin + BTLTx(Lmax - Lmin). Above this value there is no expansion, while all luminance values below this point are expanded according to: Lout = Lin + BAM x(Lin - Lt)
2.10.Display Part In the display part the conversion from digital YCRCB to analog RGB is carried out (see Fig. 2-17 on page 20). In the luminance processing path, contrast and brightness adjustments and a variety of features, such as black level expansion, dynamic peaking and soft limiting, are provided. In the chrominance path, the CRCB signals are converted to 4:4:4 format and filtered by a color transient improvement circuit. The YCRCB signals are converted by a programmable matrix to RGB color space. The display processor can switch between two separate control settings (main/side) for contrast,brightness and matrix coefficients.
2.10.1.Luminance Contrast Adjustment The contrast of the luminance signal can be adjusted by multiplication with a 6-bit contrast value. The contrast value corresponds to a gain factor from 0 to 2, where the value 32 is equivalent to a gain of 1. A second threshold, Ltr, can be programmed, above which there is no expansion. The characteristics of the black level expander are shown in Fig. 2-10and Fig. 2-11. The tilt point Lt is a function of the dynamic range of the video signal. Thus, the black level expansion is only performed when the video signal has a large dynamic range. Otherwise, the expansion to black is zero. This allows the correction of the characteristics of the picture tube.
2.10.2.Black Level Expander The black level expander enhances the contrast of the picture. Therefore the luminance signal is modified with an adjustable, non-linear function. Dark areas of
Lout
Lmax Ltr Lt BAM BTLT Lmin
a)
Lmax
Lt Lmin
b) Ltr BTHR Lin Lt
Fig. 2-10: Characteristics of the black level expander
Fig. 2-11: Black-level-expansion a) luminance input b) luminance input and output
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2.10.3.Dynamic Peaking Especially with decoded composite signals and notch filter luminance separation, as input signals, it is necessary to improve the luminance frequency characteristics. With transparent, high-bandwidth signals, it is sometimes desirable to soften the image. In the VDP 313xY, the luminance response is improved by dynamic peaking. The algorithm has been optimized regarding step and frequency response. It adapts to the amplitude of the high frequency part. Small AC amplitudes are processed, while large AC amplitudes stay nearly unmodified. The dynamic range can be adjusted from -14 to +14 dB for small high frequency signals. There is separate adjustment for signal overshoot and for signal undershoot. For large signals, the dynamic range is limited by a non-linear function that does not create any visible alias components. The peaking can be switched over to "softening" by inverting the peaking term by software.
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The center frequency of the peaking filter is switchable from 2.5 MHz to 3.2 MHz. For S-VHS and notch filter color decoding, the total system frequency responses for both PAL and NTSC are shown in Fig. 2-13. Transients, produced by the dynamic peaking when switching to the picture frame can be suppressed optionally
dB 20 15 10 5 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz
Fig. 2-12: Dynamic peaking frequency response
20 15 10 5 0 -5 -10 -15 -20 20 15 10 5 0 -5 -10 -15 -20 20 15 10 5 0 -5 -10 -15 -20
dB
20
dB
CF=3.2 MHz
15 10 5
CF=2.5 MHz
S-VHS
0 -5 -10 -15
0 dB
2
4
6
8
10
MHz
-20 20
MHz 0 dB 2 4 6 8 10
CF=3.2 MHz
15 10 5
CF=2.5 MHz
PAL/SECAM
0 -5 -10 -15
0 dB
2
4
6
8
10
MHz
-20 20
MHz 0 dB 2 4 6 8 10
CF=3.2 MHz
15 10 5
CF=2.5 MHz
NTSC
0 -5 -10 -15
MHz 0 2 4 6 8 10
-20
0
2
4
6
8
10
MHz
Fig. 2-13: Total frequency response for peaking filter and S-VHS, PAL, NTSC
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Micronas
ADVANCE INFORMATION
VDP 313xY
2.10.6.Chrominance Interpolation A linear phase interpolator is used to convert the chrominance sampling rate from 10.125 MHz (4:2:2) to 20.25 MHz (4:4:4). All further processing is carried out at the full sampling rate.
2.10.4.Digital Brightness Adjustment The DC-level of the luminance signal can be adjusted by adding/subtracting an 8-bit number in the luminance signal path in front of the softlimiter. After the brightness addition, the negative going signals are limited to zero. It is desirable to keep a small positive offset with the signal to prevent undershoots produced by the peaking from being cut.
2.10.5.Soft Limiter The dynamic range of the processed luminance signal must be limited to prevent the CRT from overload. An appropriate headroom for contrast, peaking and brightness can be adjusted by the TV manufacturer according to the CRT characteristics. All signals above this limit will be soft-clipped. A characteristic diagram of the soft limiter is shown in Fig. 2-14. The total limiter consists of three parts: 1. Part 1 includes adjustable tilt point and gain. The gain before the tilt value is 1. Above the tilt value, a part (0...15/16) of the input signal is subtracted from the input signal itself. Therefore the gain is adjustable from 16/16 to 1/16, when the slope value varies from 0 to 15. The tilt value can be adjusted from 0 to 511. 2. Part 2 has the same characteristics as part 1. The subtracting part is also relative to the input signal, so the total differential gain will become negative if the sum of slope 1 and slope 2 is greater than 16 and the input signal is above the both tilt values (see characteristics). 3. Finally, the output signal of the soft limiter will be clipped by a hard limiter adjustable from 256 to 511.
Output
511
Part 1
slope 1 [0..15]
Part 2
0 2 4 6 8 10 12 14 slope 2 [0..15]
Hard limiter
400
0 2 4 6 8 10 12 14
Calculation Example for the Softlimiter Input Amplitude. (The real signal processing in the limiter is 2 bit more than described here) Y Input Black Level Contrast Dig. Brightness BLE Peaking 16..235 (ITUR) 16 (constant) 63 20 off off
300
range= 256..511
200
100 tilt 1 [ 0..511] 0 0 100 200 300 400 500 600 700 800 900 tilt 2 [ 0..511]
Limiter input signal: (Yin-Black Level)Contr./32 + Brightn. (235-16) 63/32 + 20 = 451
Limiter Input
1023
Fig. 2-14: Characteristic of soft limiter a and b and hard limiter
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VDP 313xY
2.10.7.Chrominance Transient Improvement The intention of this block is to enhance the chrominance resolution. A correction signal is calculated by differentiation of the color difference signals. The differentiation can be selected according to the signal bandwidth, e.g. for PAL/NTSC/SECAM or digital component signals, respectively. The amplitude of the correction signal is adjustable. Small noise amplitudes in the correction signal are suppressed by an adjustable coring circuit. To eliminate `wrong colors', which are caused by over and undershoots at the chrominance transition, the sharpened chrominance signals are limited to a proper value automatically. 2.10.8.Inverse Matrix
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A 6-multiplier matrix transcodes the CR and CB signals to R-Y, B-Y, and G-Y. The multipliers are also used to adjust color saturation in the range of 0 to 2. The coefficients are signed and have a resolution of 9 bits. The matrix computes: R-Y = MR1xCB+MR2xCR G-Y = MG1xCB+MG2xCR B-Y = MB1xCB+MB2xCR The initialization values for the matrix are computed from the standard ITUR (CCIR) matrix:
L a) CR in CB in
R G B
=
1 1 1
0 -0.345 1.773
1.402 -0.713 0
Y CB CR
For a contrast setting of CTM+32, the matrix values are scaled by a factor of 64 (see Table 2-5 on page 32).
2.10.9.RGB Processing t b) Ampl. After adding the post-processed luminance, the digital RGB signals are limited to 10 bits. Three multipliers are used to digitally adjust the whitedrive. An average beam current limiter using the same multipliers is implemented (see Section 2.11.1. on page 21).
t c) CR out CB out
2.10.10.Picture Frame Generator When the picture does not fill the total screen (height or width too small) it is surrounded with black areas. These areas (and more) can be colored with the picture frame generator. This is done by switching over the RGB signal from the matrix to the signal from the internal picture frame generator.
a) CRCB input of DTI b) CRCB input + Correction signal c) sharpened and limited CRCB Fig. 2-15: Digital Color Transient Improvement
t
The width of each area (left, right, upper, lower) can be adjusted separately. The generator starts on the right, respectively lower side of the screen and stops on the left, respectively upper side of the screen. This means, it runs during horizontal, respectively vertical flyback. The color of the complete border can be programmed in the format 3 x 4 bit RGB. The contrast can be adjusted separately.
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ADVANCE INFORMATION
VDP 313xY
The signal delay can be adjusted by 3.5 clocks in half- clock steps. For the gain and filter adjustment there are two parameter sets. The switching between these two sets is done with the same RGB switch signal that is used for switching between video-RGB and OSD-RGB for the RGB outputs (see Fig. 2-16).
2.10.11.Priority Decoder The priority decoder selects between the sources video, picture frame and analog RGB (OSD). The picture frame and the OSD can be enabled independantly. The priority between picture frame and OSD is selectable. The video source always has the lowest priority. At the transitions between video and the picture frame the peaking transients can be suppressed optionally. For the video source the black level expander can be activated and a fast switch between 2 settings (main/ side) for contrast, brightness and matrix values is possible.
2.10.13.Display Phase Shifter A phase shifter is used to partially compensate the phase differences between the video source and the flyback signal. By using the described clock system, this phase shifter works with an accuracy of approximately 1 ns. It has a range of 1 clock period which is equivalent to 24.7 ns at 20.25 MHz. The large amount of phase shift (full clock periods) is realized in the front-end circuit.
2.10.12.Scan Velocity Modulation The RGB input signal of the SVM is converted to Y in a simple matrix. Then the Y signal is differentiated by a filter of the transfer function 1-Z-N, where N is programmable from 1 to 6. With a coring, some noise can be suppressed. This is followed by a gain adjustment and an adjustable limiter. The analog output signal is generated by an 8-bit D/A converter.
RGB
RGB Switch N1 N2 Coring Gain1 Gain2 Limit Delay
Matrix and Shaping Modulation Notch
Differentiator 1-Z-Nx
Coring adjustment
Gain adjustment
Limiter
Delay adjustment
D/A Converter
Output
Fig. 2-16: SVM Block diagram
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20
brightness + offset whitedrive measurement
VDP 313xY
contrast
Fig. 2-17: Digital back-end
clock prio
softlimiter luma insert for CRTmeasurement whitedrive R x beamcurr. lim.
dynamic peaking
dig. Y in Picture Frame Generator
8
display & clock control
horizontal flyback
5 CLUT, Contrast
dig. OSD in Matrix R' R
Y
dig. Rout Phase Shift 0...1 clock
10
black level expander
8
dig. CRCB in Matrix G' G DTI (Cb)
blanking for CRTmeasurement
prio CR DTI (Cr)
whitedrive G x beamcurr. lim.
dig. Gout Phase Shift 0...1 clock
10
Interpol 4:4:4
whitedrive B x beamcurr. lim.
CB
dig. Bout Phase Shift 0...1 clock B
10
side picture
PRIO decoder
main picture
select coefficients
Matrix B'
Scan Velocity Modulation
Matrix saturation
SVMout
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VDP 313xY
Cutoff and whitedrive current measurement are carried out during the vertical blanking interval. They always use the small bandwidth setting. The current range for the cutoff measurement is set by connecting a sense resistor to the MADC input. For the whitedrive measurement, the range is set by using another sense resistor and the range select switch 2 output pin (RSW2). During the active picture, the minimum and maximum beam current is measured. The measurement range can be set by using the range select switch 1 pin (RSW1) as shown in Fig. 2-1 and Fig. 2-18. The timing window of this measurement is programmable. The intention is to automatically detect letterbox transmission or to measure the actual beam current. All control loops are closed via the external control microprocessor.
2.11.Video Back End The digital RGB signals are converted to analog RGBs using three video digital to analog converters (DAC) with 10-bit resolution. An analog brightness value is provided by three additional DACs. The adjustment range is 40 % of the full RGB range. Controlling the whitedrive/analog brightness and also the external contrast and brightness adjustments is done via the Fast Processor, located in the front-end. Control of the cutoff DACs is via I2C-bus registers. Finally cutoff and blanking values are added to the RGB signals. Cutoff (dark current) is provided by three 9-bit DACs. The adjustment range is 60 % of full scale RGB range. The analog RGB-outputs are current outputs with current-sink characteristics. The maximum current drawn by the output stage is obtained with peak white RGB. An external half contrast signal can be used to reduce the output current of the RGB outputs to 50 %.
beam current A D MADC SENSE
2.11.1.CRT Measurement and Control The display processor is equipped with an 8-bit PDM-ADC for all measuring purposes. The ADC is connected to the sense input pin, the input range is 0 to 1.5 V. The bandwidth of the PDM filter can be selected; it is 40/80 kHz for small/large bandwidth setting. The input impedance is more than 1 M.
RSW1 R2 RSW2 R3 R1
Fig. 2-1: MADC Range Switches
CR + IBRM + WDRVWDR CR + IBRM black ultra black
cutoff R white drive R
R
cutoff G
CG + IBRM
G
cutoff B
CB + IBRM
B
R1||R3 RSW2 =on R1||R2||R3 RSW1=on, RSW2=on PICTURE MEAS. PMST
active measurement resistor
R1||R2||R3 RSW1=on, RSW2=on
R1
PICTURE MEAS.
TUBE MEASUREMENT TML
Lines
PMSO
Fig. 2-18: MADC Measurement Timing
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VDP 313xY
In each field two sets of measurements can be taken: a) The picture tube measurement returns results for - cutoff R - cutoff G - cutoff B - whitedrive R or G or B (sequentially) b) The picture measurement returns data on - active picture maximum current - active picture minimum current The tube measurement is automatically started when the cutoff blue result register is read. Cutoff control for RGB requires one field only while a complete whitedrive control requires three fields. If the measurement mode is set to `offset check', a measurement cycle is run with the cutoff/whitedrive signals set to zero. This allows to compensate the MADC offset as well as the input the leakage currents. During cutoff and whitedrive measurements, the average beam current limiter function (see Section 2.11.3. on page 23) is switched off and a programmable value is used for the brightness setting. The start line of the tube measurement can be programmed via I2C-bus, the first line used for the measurement, i.e. measurement of cutoff red, is 2 lines after the programmed start line. The picture measurement must be enabled by the control microprocessor after reading the min./max. result registers. If a `1' is written into bit 2 in subaddress 25, the measurement runs for one field. For the next measurement a `1' has to be written again. The measurement is always started at the beginning of active video. The vertical timing for the picture measurement is programmable, and may even be a single line. Also the signal bandwidth is switchable for the picture measurement. Two horizontal windows are available for the picture measurement. The large window is active for the entire active line. Tube measurement is always carried out with the small window. Measurement windows for picture and tube measurement are shown in Fig. 2-19.
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2.11.2.SCART Output Signal The RGB output of the VDP 313xY can also be used to drive a SCART output. In the case of the SCART signal, the parameter CLMPR (clamping reference) has to be set to 1. Then, during blanking, the RGB outputs are automatically set to 50 % of the maximum brightness. The DC offset values can be adjusted with the cutoff parameters CR, CG, and CB. The amplitudes can be adjusted with the drive parameters WDR, WDG, and WDB.
tube measurement picture meas. start active video field 1/ 2 picture meas. end
small window for tube measurement (cutoff, whitedrive)
large window for active picture picture meas. start
Fig. 2-19: Windows for tube and picture measurements
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VDP 313xY
2.11.4.Analog RGB Insertion The VDP 313xY allows insertion of 2 external analog RGB signals. Each RGB signal is key-clamped and inserted into the main RGB by the fast blank switch. The selected external RGB input is virtually handled as a priority bus signal. Thus, it can be overlaid or underlaid to the digital picture. The external RGB signals can be adjusted independently as regards DC-level (brightness) and magnitude (contrast). Which analog RGB input is selected depends on the fast blank input signals and the programming of a number of I2C-bus register settings (see Table 2-2 and Fig. 2-21). Both fast blank inputs must be either active-low or active-high. All signals for analog RGB insertion (RIN1/2, GIN1/2, BIN1/2, FBLIN1/2, HCS) must be synchronized to the horizontal flyback, otherwise a horizontal jitter will be visible. The VDP 313xY has no means for timing correction of the analog RGB input signals.
2.11.3.Average Beam Current Limiter The average beam current limiter (BCL) uses the sense input for the beam current measurement. The BCL uses a different filter to average the beam current during the active picture. The filter bandwidth is approx. 2 kHz. The beam current limiter has an automatic offset adjustment that is active two lines before the first cutoff measurement line. The beam current limiter function is located in the front-end. The data exchange between the front-end and the back-end is done via a single-wire serial interface. The beam current limiter allows the setting of a threshold current. If the beam current is above the threshold, the excess current is lowpass filtered and used to attenuate the RGB outputs by adjusting the whitedrive multipliers for the internal (digital) RGB signals, and the analog contrast multipliers for the analog RGB inputs, respectively. The lower limit of the attenuator is programmable, thus a minimum contrast can always be set. During the tube measurement, the ABL attenuation is switched off. After the whitedrive measurement line it takes 3 lines to switch back to BCL limited drives and brightness. Typical characteristics of the ABL for different loop gains are shown in Fig. 2-20; for this example the tube has been assumed to have square law characteristics.
Table 2-2: RGB Input Selection
FBFOH1=0, FBFOH2=0, FBFOL1=0, FBFOL2=0 FBLIN1 0 0 1 1 1 0 0 0 1 1 FBLIN2 0 1 0 1 1 0 0 1 0 1 FBPOL 0 0 0 0 0 1 1 1 1 1 FBPRIO x x x 0 1 0 1 x x x RGB output Video RGB input 2 RGB input 1 RGB input 1 RGB input 2 RGB input 1 RGB input 2 RGB input 1 RGB input 2 Video
Fig. 2-20: Beam current limiter characteristics: beam current output vs. drive BCL threshold: 1
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VDP 313xY
2.11.5.Fast Blank Monitor The presence of external analog RGB sources can be detected by means of a fast blank monitor. The status of the selected fast blank input can be monitored via an I2C bus register. There is a 2 bit information, giving static and dynamic indication of a fast blank signal. The static bit is directly reading the fast blank input line, whereas the dynamic bit is reading the status of a flip-flop triggered by the negative edge of the fast blank signal. With this monitor logic it is possible to detect if there is an external RGB source active and if it is a full screen insertion or only a box. The monitor logic is connected directly to the FBLIN1 or FBLIN2 pin. Selection is done via I2C bus register. 2.11.7.IO Port Expander
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The VDP 313xY provides a general purpose IO port to control and monitor up to seven external signals. The port direction is programmable for each bit individually. Via I2C bus register it is possible to write or read each port pin. Because of the relatively low I2C bus speed, only slow or static signals can be handled.
2.11.6. Half Contrast Control Insertion of transparent text pages or OSD onto the video picture is often difficult to read, especially if the video contrast is high. The VDP 313xY allows contrast reduction of the video background by means of a half contrast input (HCS pin). This input can be supplied with a fast switching signal (similar to the fast blank input), typically defining a rectangular box in which the video picture is displayed with reduced contrast. The analog RGB inputs are still displayed with full contrast.
FBFOH1 FBFOL1
FBPOL
FBPRIO
HCSPOL
FBLIN1
HCS # FB Fast int Blank Selection # # HCS intern
Fast Blank Monitor FBLIN2
HCSEN HCSFOH Fig. 2-22: Half Contrast Switch Logic
FBFOH2 FBFOL2 FBMON Fig. 2-21: Fast Blank Selection Logic
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VDP 313xY
digital SVM in 8
8 bit DAC SVM 1.88 mA 0.94 mA
int. brightness * whitedrive R
analog SVM out
HCS
9 bit DAC 1.5 mA 9 bit DAC 2.2 mA
cutoff R
digital R in 10
10 bit DAC Video 3.75 mA
int. brightness * whitedrive G
blanking 750 A analog R out
9 bit DAC 1.5 mA 9 bit DAC 2.2 mA
cutoff G
digital G in 10
10 bit DAC Video 3.75 mA
int. brightness * whitedrive B
blanking 750 A analog G out
9 bit DAC 1.5 mA
cutoff B
digital B in 10
10 bit DAC Video 3.75 mA
9 bit DAC 2.2 mA
blanking 750 A analog B out
H
ext. brightness * whitedrive R ext. brightness * whitedrive G ext. brightness * whitedrive B
V
serial interface
9 bit DAC 1.5 mA
9 bit DAC 1.5 mA
9 bit DAC 1.5 mA
blank & measurem. timing
whitedrive R whitedrive G
ext. contrast * whitedrive R * beam current lim.
ext. contrast * whitedrive G * beam current lim.
whitedrive B int . brightness ext. contrast ext. brightness
9 bit U/I-DAC 3.75 mA clamp & mux
9 bit U/I-DAC 3.75 mA clamp & mux
ext. contrast * whitedrive B * beam current lim.
9 bit U/I-DAC 3.75 mA clamp & mux FBL prio
8 bit ADC measurm.
key
1 2 analog R in
1 2 analog G in
1 2 analog B in
1 2 fast blank in
Sense Input
Fig. 2-23: Video back-end
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measurement buffer
I/O
25
VDP 313xY
2.12.Synchronization and Deflection The synchronization and deflection processing is distributed over front-end and back-end. The video clamping, horizontal and vertical sync separation and all video related timing information are processed in the front-end. Most of the processing that runs at the horizontal frequency is programmed on the internal Fast Processor (FP). Also the values for vertical and East/West deflection are calculated by the FP software. The information extracted by the video sync processing is multiplexed onto the hardware front sync signal (FSY) and distributed internally to the rest of the video processing system. The data for the vertical deflection, the sawtooth and the East/West correction signal is calculated in the front end. The data is transferred to the back-end by a single wire interface. The display related synchronization, i.e. generation of horizontal and vertical drive and synchronization of horizontal and vertical drive to the video timing
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extracted in the front-end, are implemented in hardware in the back-end.
2.12.1. Deflection Processing The deflection processing generates the signals for the horizontal and vertical drive (see Fig. 2-24). This block contains two phase-locked loops: - PLL2 generates the horizontal and vertical timing, e.g. blanking, clamping and composite sync. Phase and frequency are synchronized by the front sync signal. - PLL3 adjusts the phase of the horizontal drive pulse and compensates for the delay of the horizontal output stage. Phase and frequency are synchronized by the oscillator signal of PLL2. The horizontal drive circuitry uses a digital sine wave generator to produce the exact (subclock) timing for the drive pulse. The generator runs at 1 MHz; in the output stage the frequency is divided down to give drive-pulse period and width. The horizontal drive uses an open drain output transistor.
HFLB
PLL3
skew measurement phase comparator & lowpass DCO sinewave generator DAC & LPF 1:64 & output stage
HOUT
+
angle & bow
blanking, clamping, etc.
MSY
main sync generator front sync interface
display timing phase comparator & lowpass
PLL2
sync generation DCO line counter
CSY VS INTLC
FSY
vertical reset
clock & control
VPROT
E/W correction
PWM 15 bit
EW
VDATA
vertical serial data sawtooth PWM 15 bit
VERT VERTQ
Fig. 2-24: Deflection processing block diagram
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Micronas
ADVANCE INFORMATION
VDP 313xY
Note: The processing delay of the internal digital video path differs depending on the comb filter option of the VDP 313xY. The versions with comb filter have an additional delay of 34 clock cycles.
2.12.2.Angle & Bow Correction The Angle & Bow correction is part of the horizontal drive PLL. This feature allows a shift of the horizontal drive pulse phase depending on the vertical position on the screen. The phase correction has a linear (angle) and a quadratic term (bow).
2.12.4.Vertical and East/West Deflection The calculations of the vertical and East/West deflection waveforms is done by the internal Fast Processor (FP). The algorithm uses a chain of accumulators to generate the required polynomial waveforms. To produce the deflection waveforms, the accumulators are initialized at the beginning of each field. The initialization values must be computed by the TV control processor and are written to the front-end once. The waveforms are described as polynomials in x, where x varies from 0 to 1 for one field.
2.12.3.Horizontal Phase Adjustment This section describes a simple way to align PLL phases and the horizontal frame position. 1. With HDRV the duration of the horizontal drive pulse has to be adjusted 2. With POFS2 the delay between input video and display timing (e.g. clamping pulse for analog RGB) has to be adjusted 3. With CSYDEL the delay between video and analog RGB (OSD) has to be adjusted. 4. With CSYDEL and HPOS the horizontal position of both, the digital and analog RGB signal (from SCART) relative to the clamping pulse has to be adjusted to the correct position, e.g. the pedestal of the generator signal. 5. With POFS3 the position of horizontal drive/flyback relative to RGB has to be adjusted 6. With NEWLIN the position of a scaled video picture can be adjusted (left, middle, center, etc; versions with panorama scaler only). 7. With HBST and HBSO, the start and stop values for the horizontal blanking have to be adjusted.
P: a + b(x-0.5) + c(x-0.5)2 + d(x-0.5)3 + e(x-0.5)4
The initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for East/West deflection are 12-bit values. Fig. 2-25 shows several vertical and East/West deflection waveforms. The polynomial coefficients are also stated. In order to get a faster vertical retrace timing, the output impedance of the vertical D/A-converter is reduced during the retrace.
Vertical:
a,b,c,d 0,1,0,0 0,1,1,0 0,1,0,1
East/West:
a,b,c,d,e 0,0,1,0,0 0,0,0,0,1 0,0,1,1,1
Fig. 2-25: Vertical and East/West Deflection Waveforms
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VDP 313xY
2.12.5.EHT Compensation The vertical waveform can be scaled according the average beam current. This is used to compensate the effects of electric high tension changes due to beam current variations. EHT compensation for East/West deflection is done with an offset corresponding to the average beam current. 2.13.Reset and Power On
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Reset of most VDP 313xY functions is performed by the RESQ pin. When this pin becomes active all internal registers and counters are lost. When the RESQ pin is released, the internal reset is still active for 4 s. After that time, the initialization of all required registers is performed by the internal Fast Processor. The VDP 313xY has clock and voltage supervision circuits to generate a stable HOUT signal. The voltage supervision activates an internal reset signal when the supply for the digital circuits (VSUPD) goes below ~2.5 V for more than 50 ns. This reset signal is extended by 50 s after VSUPD is back again. After power on or reset the HOUT generation is switched to a freerunning mode with a fix duty cycle of 50 %. For normal operation the EHPLL bit has to be set first. During the switch the actual period of HOUT can vary by up to 1 s.
2.12.6.Protection Circuitry - Picture tube and drive stage protection is provided through the following measures: - Vertical flyback protection input: this pin searches for a negative edge in every field, otherwise the RGB drive signals are blanked. - Drive shutoff during flyback: this feature can be selected by software. - Safety input pin: this input has two thresholds. Between zero and the lower threshold, normal functioning takes place. Between the lower and the higher threshold, the RGB signals are blanked. Above the higher threshold, the RGB signals are blanked and the horizontal drive is shut off. Both thresholds have a small hysteresis. - The main oscillator and the horizontal drive circuitry are run from a separate (standby) power supply and are already active while the TV set is powering up.
Reset Internal Reset Initialization
4s
approx. 60s
Fig. 2-26: External Reset
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Micronas
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VDP 313xY
Table 2-3: I2C Chip Addresses
Chip Address front-end back-end A6 1 1 A5 0 0 A4 0 0 A3 0 0 A2 1 1 A1 1 0 A0 1 1 R/W 1/0 1/0
2.14.Serial Interface 2.14.1.I2C-Bus Interface Communication between the VDP and the external controller is done via I2C-bus. The VDP has two I2C-bus slave interfaces (for compatibility with VPC/ DDP applications) - one in the front-end and one in the back-end. Both I2C-bus interfaces use I2C clock synchronization to slow down the interface if required. Both I2C-bus interfaces use one level of subaddress: the I2C-bus chip address is used to address the IC and a subaddress selects one of the internal registers. The I2C-bus chip addresses are given below:
The registers of the VDP have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. Fig. 2-27 shows I2C-bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set.
S
1000 111
W Ack
FPWR
Ack
send FP-addressbyte high
Ack
send FP-addressbyte low
Ack P
I2C write access to FP
S
1000 111
W Ack
FPDAT
Ack
send databyte high
Ack
send databyte low
Ack P
S
1000 111
W Ack
FPRD
Ack
send FP-addressbyte high
Ack
send FP-addressbyte low
Ack P
I2C read access to FP
S
1000 111
W Ack
FPDAT
Ack S
1000 111
R Ack
receive databyte high receive databyte low
Ack Nak P
S
1000 111
W Ack
0111 1100
Ack 1 or 2 byte Data
P
I2C write access subaddress 7c I2C read access subaddress 7c
S
1000 111
W Ack
0111 1100
Ack S
1000 111
R Ack high byte Data Ack low byte Data Nak P W R Ack Nak S P = = = = = =
SDA S SCL Fig. 2-27: I2C-bus protocols
1 0 P
0 1 0 1 Start Stop
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2.14.2.Control and Status Registers Table 2-4 gives definitions of the VDP control and status registers. The number of bits indicated for each register in the table is the number of bits implemented in hardware, i.e. a 9-bit register must always be accessed using two data bytes but the 7 MSB will be `don't care' on write operations and `0' on read operations. Write registers that can be read back are indicated in Table 2-4. Functions implemented by software in the on-chip control microprocessor (FP) are explained in Table 2-6.
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A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in Table 2-4. The register modes given in Table 2-4 are - w: write only register - w/r:write/read data register - r: read data from VPC
- v: register is latched with vertical sync - h: register is latched with horizontal sync
Table 2-4: I2C control and status registers of the video frontend
I2C Sub address (hex) FP Interface 35 8 r FP status bit[0] bit[1] bit[2] 36 16 w bit[8:0] bit[11:9] 37 16 w bit[8:0] bit[11:9] 38 16 w/r bit[11:0] write request read request busy 9-bit FP read address reserved, set to zero 9-bit FP write address reserved, set to zero FP data register, reading/writing to this register will autoincrement the FP read/write address. Only 16 bit of data are transferred per I2C teleramm. FPDAT FPWR FPRD FPSTA Number of bits Mode Function Default (hex) Name
Black Line Detector 12 16 r read only register, do not write to this register! after reading, LOWLIN and UPLIN are reset to 127 to start a new measurement bit[6:0] bit[7] bit[14:8] bit[15] number of lower black lines always 0 number of upper black lines normal/black picture UPLIN BLKPIC - BLKLIN LOWLIN
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VDP 313xY
Table 2-4: I2C control and status registers of the video frontend
I2C Sub address (hex) Miscellaneous 29 16 w/r Test pattern generator: bit[10:0] bit[11] bit[13:12] 00 01 10 11 bit[15:14] 0/1 22 16 w/r 0/1 reserved (set to 0) disable/enable test pattern generator output mode: Y/C = ramp (240 ... 17) Y/C = 16 Y/C = 90 Y/C = 240 reserved (set to 0) 0 0 0 TPGEN TPGMODE TPG Number of bits Mode Function Default (hex) Name
0 NEWLIN 50
NEWLINE (available for versions with panorama scaler only): bit[10:0] NEWLINE register This register defines the readout start of the next line in respect to the value of the sync counter. Value of this register must be greater than 31 for correct operation. reserved (set to 0)
bit[15:11]
Micronas
31
VDP 313xY
Table 2-5: I2C control and status registers of the video backend (Registers are set to '0' at reset, default values are recommendations)
I2C Sub address (hex) Luminance Channel 61 65 51 55 7D 59 9 9 9 9 9 9 wv wv wv wv wv wv bit[5:0] bit[5:0] bit[8:0] bit[8:0] bit[7] 0..63/32 0..63/32 main contrast setting side contrast setting 32 32 0 0 0 Number of bits Mode Function
ADVANCE INFORMATION
Default (hex)
Name
CTM CTS BRM BRS BLE BLE1
-256..255 main brightness setting -256..255 side brightness setting 0/1 enable/disable black level expander
black level expander: bit[3:0] bit[8:4] 0..15 0...31 tilt coefficient amount 8 12
BTLT BAM BLE2
5D
9
wv
black level expander: bit[8:0] 0..511 disable expansion, threshold value 200
BTHR BLE3
73
9
wv
black level expander measurement bit[7:0] bit[8] 0..255 0/1 vstart 50/60 Hz measurement windowlength 0 15
BWL BVST
start line = vstart stop line = 336/283 - vstart (or vertical sync) 69 9 wv luma peaking filter, the gain at high frequencies and small signal amplitudes is: 1 + (k1+k2)/8 bit[3:0] bit[7:4] bit[8] 6D 9 wv 0..15 0..15 0/1 k1: peaking level undershoot k2: peaking level overshoot peaking value normal/inverted (peaking/softening) 4 4 0 PK1 PKUN PKOV PKINV PK2 3 0 COR PFS LSL1 0 0 LSLSA LSLSB LSL2 255 1 LSLAL LSLM
luma peaking filter, coring bit[4:0] bit[7:5] bit[8] 0/1 0..31 coring level reserved peaking filter center frequency high/low
41
9
wv
luma soft limiter, slope A and B bit[3:0] bit[7:4] slope segment A slope segment B
45
9
wv
luma soft limiter, absolute limit bit[7:0] bit[8] 0/1 luma soft limiter absolute limit (unsigned) modulation off/on 250 300
4D 49
9 9
wv wv
bit[8:0] bit[8:0]
luma soft limiter segment A tilt point (unsigned) luma soft limiter segment B tilt point (unsigned)
LSLTA LSLTB
32
Micronas
ADVANCE INFORMATION
VDP 313xY
Table 2-5: I2C control and status registers of the video backend (Registers are set to '0' at reset, default values are recommendations)
I2C Sub address (hex) Chrominance Channel 14 8 w/r luma/chroma matching delay bit[2:0] bit[7:3] 5E 9 wv -3...3 variable chroma delay 0 reserved, set to 0 DTI 1 5 1 DTICO DTIGA DTIMO LCM CDEL Number of bits Mode Function Default (hex) Name
digital transient improvement bit[3:0] bit[7:4] bit[8] 0..15 0..15 0/1 coring value DTI gain narrow/wide bandwidth mode
Inverse Matrix main matrix coefficient R-Y = MR1MxCB+MR2MxCR 7C 74 9 9 wv wv bit[8:0] bit[8:0] -256/128 ... 255/128 -256/128 ... 255/128 -256/128 ... 255/128 -256/128 ... 255/128 -256/128 ... 255/128 -256/128 ... 255/128 -256/128 ... 255/128 -256/128 ... 255/128 -256/128 ... 255/128 -256/128 ... 255/128 -256/128 ... 255/128 -256/128 ... 255/128 0 86 MR1M, MR2M
main matrix coefficient G-Y = MG1MxCB+MG2MxCR 6C 64 9 9 wv wv bit[8:0] bit[8:0] -22 -44 MG1M, MG2M
main matrix coefficient B-Y = MB1MxCB + MB2MxCR 5C 54 9 9 wv wv bit[8:0] bit[8:0] 113 0 MB1M, MB2M
side matrix coefficient R-Y = MR1SxCB + MR2SxCR 78 70 9 9 wv wv bit[8:0] bit[8:0] 0 73 MR1S, MR2S
side matrix coefficient G-Y = MG1SxCB + MG2SxCR 68 60 9 9 wv wv bit[8:0] bit[8:0] -19 -37 MG1S, MG2S
side matrix coefficient B-Y = MB1SxCB + MB2SxCR 58 50 9 9 wv wv bit[8:0] bit[8:0] 97 0 MB1S, MB2S
Micronas
33
VDP 313xY
Table 2-5: I2C control and status registers of the video backend (Registers are set to '0' at reset, default values are recommendations)
I2C Sub address (hex) Picture Frame Generator 47 9 wv bit[7:0] bit[8] reserved, set t o zero 1 enable picture frame generator 0 Number of bits Mode Function
ADVANCE INFORMATION
Default (hex)
Name
PFGEN PFC 0 0 0 PFCB PFCG PFCR PFRCT 8
picture frame color 12 bit wide, 11 16 wh bit[3:0] bit[7:4] bit[11:8] 0..15 0..15 0..15 blue amplitude green amplitude red amplitude
picture frame insertion contrast for R (ampl. range: 0 to 255) 4C 9 wv bit[3:0] bit[7:4] reserved, set to zero 0..13 14,15 R amplitude = PFCR x (PFRCT + 4) invalid
picture frame insertion contrast for G (ampl. range: 0 to 255) 48 9 wv bit[3:0] bit[7:4] reserved, set to zero 0..13 14,15 G amplitude = PFCG x (PFGCT + 4) invalid 8
PFGCT
picture frame insertion contrast for B (ampl. range: 0 to 255) 44 9 wv bit[3:0] bit[7:4] reserved, set to zero 0..13 14,15 4F 9 wv B amplitude = PFCB x (PFBCT + 4) invalid 0 8
PFBCT
bit[8:0] horizontal picture frame begin code 0 = picture frame generator horizontally disabled code 1FF = full frame bit[8:0] horizontal picture frame end
PFGHB
53 63 6F
9 9 9
wv wv wv
0 270 56
PFGHE PFGVB PFGVE
bit[8:0] vertical picture frame begin code 0 = picture frame generator vertically disabled bit[8:0] vertical picture frame end
Priority Decoder 75 79 9 9 wv wv bit[7] bit[7] 0/1 0/1 select main/side setting for contrast,brightness,matrix disable/enable peaking transient suppression when signal is switched to the picture frame 0 0 SIDE PKTRNS
34
Micronas
ADVANCE INFORMATION
VDP 313xY
Table 2-5: I2C control and status registers of the video backend (Registers are set to '0' at reset, default values are recommendations)
I2C Sub address (hex) Scan Velocity Modulation 5A 9 wv video mode coefficients bit[5:0] bit[8:6] 52 9 wv limiter bit[6:0] bit[8:5] 4E 9 wv limit value not used, set to "0" 100 0 SVM4 7 0 SVDEL SVCOR gain1 differentiator delay 1 (0= filter off, 1...6= delay) 60 4 SVM1 SVG1 SVD1 SVM3 SVLIM Number of bits Mode Function Default (hex) Name
delay and coring bit[3:0] bit[7:4] bit[8] adjustable delay, in 1/2 display clock steps, coring value not used, set to "0"
Display Controls 4A 46 42 9 9 9 wv wv wv cutoff Red cutoff Green cutoff Blue 0 0 0 CR CG CB
Micronas
35
VDP 313xY
Table 2-5: I2C control and status registers of the video backend (Registers are set to '0' at reset, default values are recommendations)
I2C Sub address (hex) Tube- and Picture-Measurements 7B 9 wv picture measurement start line bit[8:0] 6B 9 wv (TML+9)..511 first line of picture measurement 23 Number of bits Mode Function
ADVANCE INFORMATION
Default (hex)
Name
PMST
picture measurement stop line bit[8:0] (PMST+1)..511 last line of picture measurement 308
PMSO
7F
9
wv
tube measurement line bit[8:0] 0..511 start line for tube measurement 15 0
TML
25
8
w/r
tube and picture measurement control bit[0] bit[1] bit[2] 0/1 0/1 0/1 disable/enable tube measurement 80/40 kHz bandwidth for picture measurement disable/enable picture measurement (writing a '1' starts one measurement cycle) large/small picture measurement window, will be disabled from bit[3] in address h'32 measure / offset check for adc reserved
PMC TMEN PMBW PMEN
bit[3]
0/1
PMWIN
bit[4] bit[7:5] 13 16 w/r
0/1
OFSEN
white drive measurement control bit[9:0] bit[10] bit[11] 0/1 0..1023 RGB values for white drive beam current measurement reserved RGB values for white drive beam current measurement disabled/ enabled 0 512
WDM WDRV
EWDM
8 18 19 1A 1D 1C 1B
r
measurement result registers minimum in active picture maximum in active picture white drive cutoff/leakage red cutoff/leakage green cutoff/leakage blue, read pulse starts tube measurement
- MRMIN MRMAX MRWDR MRCR MRCG MRCB
36
Micronas
ADVANCE INFORMATION
VDP 313xY
Table 2-5: I2C control and status registers of the video backend (Registers are set to '0' at reset, default values are recommendations)
I2C Sub address (hex) 1E 8 r measurement adc status and fast blank input status measurement status register bit[0] bit[2:1] 00 01 10 11 bit[3] bit[4] bit[5] 0/1 0/1 1 0/1 tube measurement active / complete white drive measurement cycle red green blue reserved picture measurement active / complete fast blank input low / high (static) fast blank input negative transition since last read (bit reset at read) reserved Number of bits Mode Function Default (hex) - PMS Name
bit[7:6] Vertical Timing 67 9 wv vertical blanking start bit[8:0] 77 9 wv 0..511
VBST first line of vertical blanking 305 VBSO last line of vertical blanking 25 309 VPER
vertical blanking stop bit[8:0] 0..511
5F
9
wv
free running field period bit[8:0] period = (value+4) lines
Horizontal Deflection and Timing 76 9 wv linear term of angle & bow correction bit[8:0] 7A 9 wv -256..+255 500 ns 0 BOW -256..+255 500 ns -141 POFS2 0 ANGLE
quadratic term of angle & bow correction bit[8:0]
6E
9
wv
adjustable delay of PLL2, clamping, and blanking (relative to front sync) bit[8:0] -256..+255 8 s
72
9
wv
adjustable delay of horizontal drive & flyback (relative to PLL2) bit[8:0] -256..+255 8 s
0
POFS3
7E
9
wv
adjustable delay of main sync (relative to PLL2) adjust horizontal position for digital picture bit[8:0] 20 steps=1 s
120
HPOS
5B
9
wv
start of horizontal blanking bit[8:0] 0..511
1
HBST
57
9
wv
end of horizontal blanking bit[8:0] 0..511
48
HBSO
Micronas
37
VDP 313xY
Table 2-5: I2C control and status registers of the video backend (Registers are set to '0' at reset, default values are recommendations)
I2C Sub address (hex) PLL2/3 filter coefficients, 1of5 bit code (n+ set bit number) 62 66 6A 15 9 9 9 16 wv wv wv w/r bit[5:0] bit[5:0] bit[5:0] proportional coefficient PLL3, 2-n-1 proportional coefficient PLL2, 2 integral coefficient PLL2, 2-n-5
-n-1
ADVANCE INFORMATION
Number of bits
Mode
Function
Default (hex)
Name
2 1 2
PKP3 PKP2 PKI2 HVC
horizontal drive and vertical signal control register bit[5:0] bit[6] bit[7] bit[8] bit[9] bit[10] bit[11] bit[12] 0..63 0/1 0/1 0/1 0/1 0/1 0/1 0/1 horizontal drive pulse duration in s (internally limited to 4..61) disable/enable horizontal PLL2 and PLL3 1: disable horizontal drive pulse during flyback reserved, set to '0' enable/disable ultra black blanking 0: all outputs blanked 1: normal mode enable/disable clamping for analog RGB input disable/enable vertical free running mode (FIELD is set to field2, no interlace) enable/disable vertical protection disable/enable phase shift of display clock 32 0 0 0 0 1 0 0
HDRV EHPLL EFLB
DUBL EBL DCRGB SELFT
bit[13] bit[14] bit[15] 9D 8 w/r
0/1 0/1
0 0 1 0
DVPR DISKA SYCTRL
reserved (set to 0)
sync output control bit[0] bit[1] bit[2] bit[3] bit[4] bit[5] invert INTLC disable INTLC (tristateINTLC output) invert VS disable VS disable CSY force INTLC to polarity defined in 'INTLCINV'
9E
8
w/r
delay of CSY output (relative to PLL2) bit[7:0] -128..127 8 s
0
CSYDEL
38
Micronas
ADVANCE INFORMATION
VDP 313xY
Table 2-5: I2C control and status registers of the video backend (Registers are set to '0' at reset, default values are recommendations)
I2C Sub address (hex) Analog RGB Insertion 4B 4B 32 9 9 8 wv wv w/r bit[7] bit[0] 0/1 0 1 disable/enable analog fast blank input for RGB inserion Picture frame overOSD OSD over picture frame 0 0 0 ERGB OSDPRIO FBMOD FBFOH1 Number of bits Mode Function Default (hex) Name
fast blank interface mode bit[0] 0 1 bit[1] bit[2] bit[3] 0/1 0/1 1 internal fast blank 1 from FBLIN1 pin force internal fast blank 1 signal to high internal fast blank active high/low disable/enable clamping reference for RGB outputs full line MADC measurement window, disables bit [3] in address 25 horizontal flyback input active high/low reserved (set to 0) 0 1 internal fast blank 1 from FBLIN1 pin force internal fast blank 1 signal to low
FBPOL CLMPR FLMW
bit[4] bit[6:5] bit[7]
0/1
FLPOL
FBFOL1
31
8
w/r
fast blank interface mode 2 bit[0] 0 1 bit[1] 0 1 bit[2] internal fast blank 2 from FBLIN2 pin force internal fast blank 2 signal to high internal fast blank 2 from FBLIN2 pin force internal fast blank 2signal to low
0
FBMOD2 FBFOH2
FBFOL2
fast blank input priority 0 FBLIN1>FBLIN2 1 FBLIN2>FBLIN1 fast blank monitor input select 0 monitor connected to FBLIN1 pin 1 monitor connected to FBLIN2 pin half contrast switch enable 0/1 HCS disable/enable 0 1 0/1 half contrast from HCS pin force half contrast signal to high half contrast active high/low at HCS pin reserved (set to 0)
FBPRIO
bit[3]
FBMON
bit[4] bit[5] bit[6] bit[7]
HCSEN HCSFOH HCSPOL
Micronas
39
VDP 313xY
Table 2-5: I2C control and status registers of the video backend (Registers are set to '0' at reset, default values are recommendations)
I2C Sub address (hex) 10 8 w/r Sync Output bit[5:0] bit[7:6] 00 01 10 11 Ports 34 16 w/r IO Port bit[6:0] bit[7] bit[14:8] 0 1 bit[15] Hardware ID 9F 16 r Hardware version number bit[7:0] bit[15:8] hardware id (A3 = 13, B1 = 21 a.s.o.) product code VDP 31xx Y (e.g. 32 for VDP 3132 Y) data to/from PORT[6:0] reserved (set to 0) port direction switch PORT[bit-8] to input switch PORT[bit-8] to output reserved (set to 0) 0 reserved (set to 0) function of CSY pin composite sync signal output 25 Hz output (field1/field2 signal) horizontal sync signal output 1 MHz horizontal drive clock 0 Number of bits Mode Function
ADVANCE INFORMATION
Default (hex)
Name
CSYM
IOPORT IODATA IODIR
read only
HWID
40
Micronas
ADVANCE INFORMATION
VDP 313xY
Table 2-6: Control Registers of the Fast Processor for control of the video frontend functions -default values are initializied at reset
FP Subaddress
(hex)
Function
Default
(hex)
Name
Standard Selection 20 Standard select: bit[2:0] standard 0 PAL B,G,H,I (50 Hz) 1 NTSC M (60 Hz) 2 SECAM (50 Hz) 3 NTSC44 (60 Hz) 4 PAL M (60 Hz) 5 PAL N (50 Hz) 6 PAL 60 (60 Hz) 7 NTSC COMB (60 Hz) 0/1 4.433618 3.579545 4.286 4.433618 3.575611 3.582056 4.433618 3.579545 0 STD PAL NTSC SECAM NTSC44 PALM PALN PAL60 NTSCC SDTMOD
bit[3]
standard modifier PAL modified to simple PAL NTSC modified to compensated NTSC SECAM modified to monochrome 625 NTSCC modified to monochrome 525
bit[4] bit[5] bit[6]
reserved (set to 0) 0/1 0/1 2-H comb filter off/on S-VHS mode off/on (2-H comb is switched off) COMB SVHS SDTOPT
Option bits allow to suppress parts of the initialization, this can be used for color standard search: bit[7] bit[8] bit[9] bit[10] bit[11] no hpll setup no vertical setup no acc setup 2-H comb filter set-up only status bit, normally write 0. After the FP has switched to a new standard, this bit is set to 1 to indicate operation complete. Standard is automatically initialized when the insel register is written.
Micronas
41
VDP 313xY
ADVANCE INFORMATION
Table 2-6: Control Registers of the Fast Processor for control of the video frontend functions -default values are initializied at reset
FP Subaddress
(hex)
Function
Default
(hex)
Name
148
Enable automatic standard recognition (ASR) bit[0] bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] bit[10:7] bit[11] 0/1 0/1 0/1 0/1 0/1 0/1 0/1 PAL B,G,H,I (50 Hz) NTSC M SECAM NTSC44 PAL M PAL N PAL 60 (60 Hz) (50 Hz) (60 Hz) (60 Hz) (50 Hz) (60 Hz) 4.433618 3.579545 4.286 4.433618 3.575611 3.582056 4.433618
0
ASR_ENA
reserved set to 0 1 reset status information `switch' in asr_status (cleared automatically)
0: disable recognition; 1: enable recognition Note: For correct operation don't change FP reg. 20h and 21h, while ASR is enabled! 14E Status of automatic standard recognition bit[0] bit[1] bit[2] bit[3] bit[4] bit[5] bit[4:0] 1 1 1 1 1 1 error of the vertical standard (neither 50 nor 60 Hz) detected standard is disabled search active search terminated, but failed no color found standard has been switched (since last reset of this flag with bit[11] of asr_enable) 0 ASR_STATUS VWINERR DISABLED BUSY FAILED NOCOLOR SWITCH
00000 all ok 00001 search not started, because vwin error
detected (no input or SECAM L)
00010 search not started, because detected vert.
standard not enabled
0x1x0 search started and still active 01x00 search failed (found standard not correct) 01x10 search failed, (detected color standard not
enabled)
1000 no color found (monochrome input or switch
betw. CVBS/SVHS necessary) 22 picture start position, this register sets the start point of active video, this can be used e.g. for panning. The setting is updated when 'sdt' register is updated. 0 SFIF
42
Micronas
ADVANCE INFORMATION
VDP 313xY
Table 2-6: Control Registers of the Fast Processor for control of the video frontend functions -default values are initializied at reset
FP Subaddress
(hex)
Function
Default
(hex)
Name
23
luma/chroma delay adjust. The setting is updated when 'sdt' register is updated. bit[5:0] bit[11:6] reserved, set to zero luma delay in clocks, allowed range is +1...-7 writing to this register will also initialize the standard 00 01 10 11 bit[2] 0 1 bit[4:3] 00 01 10 11 bit[6:5] 00 01 10 11 bit[7] bit[8] bit[10:9] 0/1 0/1 luma selector VIN1 VIN2 VIN3 VIN4 chroma selector CIN1 CIN2 IF compensation off 6 dB/Okt 12 dB/Okt 10 dB/MHz only for SECAM chroma bandwidth selector narrow normal broad wide adaptive/fixed SECAM notch filter enable luma lowpass filter
0
LDLY
21
Input select: bit[1:0]
INSEL 00 VIS
0
CIS
00
IFC
01
CBW
FNTCH LOWP HPLLMD
hpll speed 00 no change 01 terrestrial 10 vcr 11 mixed status bit, write 0, this bit is set to 1 to indicate operation complete.
bit[11]
Micronas
43
VDP 313xY
ADVANCE INFORMATION
Table 2-6: Control Registers of the Fast Processor for control of the video frontend functions -default values are initializied at reset
FP Subaddress
(hex)
Function
Default
(hex)
Name
2F
YCRCB mode control register bit[6:0] bit[7] bit[8] bit[9] reserved (set to 0) 1 ADC over-/underflow (has to be reset after read if used) 0 1 disable YCRCB enable YCRCB
0
YCRCB
ADC range 0 nominal input amplitude (350 mV) 1 extented input amplitude (500 mV) reserved (set to 0)
bit[11:10]
Note: Activate the YCRCB mode by - enabling YCRCB - selecting simple PAL or NTSC M, svhs=1, comb=0 in the std register - setting cbw=2 in the insel register Comb Filter 27 comb filter control register bit[0] 0 1 bit[1] 0 1 bit[2] bit[4:3] bit[6:5] bit[11:7] 0 1 0..3 0..3 comb coefficients are calculated for luma/ chroma comb coefficients for luma are used for luma and chroma luma comb strength depends on signal amplitude luma comb strength is independent of amplitude max comb booster reduced comb booster comb strength for chroma signal comb strength for luma signal 0 CMB_UC CC
0
DAA
1 3 2 0
KB KC KY CLIM
0..31 overall limitation of the calculated comb coefficients 0 no limitation 31 max limitation (1/2)
44
Micronas
ADVANCE INFORMATION
VDP 313xY
Table 2-6: Control Registers of the Fast Processor for control of the video frontend functions -default values are initializied at reset
FP Subaddress
(hex)
Function
Default
(hex)
Name
Color Processing 30 Saturation control bit[11:0] 17A bit[10:0] bit[11] 39 bit[10:0] bit[11] 3A DC DVCO F8 F9 crystal oscillator center frequency adjust, -2048...2047 crystal oscillator center frequency adjustment value for line lock mode,true adjust value is DVCO - ADJUST. For factory crystal alignment, using standard video signal: set DVCO = 0, set lock mode, read crystal offset from ADJUST register and use negative value for initial center frequency adjustment via DVCO. F7 crystal oscillator line-locked mode, lock command/status write: 100 0 read: 0 >2047 B5 enable lock disable lock unlocked locked 400 AUTOLOCK 0 XLCK -720 read only DVCO ADJUST 0...4094 (2070 corresponds to 100% saturation) 4095 disabled (test mode only) 0...2047 CR-attenuation 0/1 disable/enable CR-attenuation 1591 o 25 0 5 0 KILHY TINT CR_ATT CR_ATT_ENA KILVL 2070 ACC_SAT
0...2047 amplitude killer level (0: killer disabled) 0/1 disable/enable chroma ADC
amplitude killer hysteresis NTSC tint angle, 512 = /4
crystal oscillator line-locked mode, autolock feature. If autolock is enabled, crystal oscillator locking is started automatically. bit[11:0] threshold; 0: autolock off
Micronas
45
VDP 313xY
ADVANCE INFORMATION
Table 2-6: Control Registers of the Fast Processor for control of the video frontend functions -default values are initializied at reset
FP Subaddress
(hex)
Function
Default
(hex)
Name
FP Status Register 12 general purpose control bits bit[2:0] bit[3] bit[8:4] bit[9] bit[11:10] reserved, do not change vertical standard force reserved, do not change disable flywheel interlace reserved, do not change 1 DFLW 0 VFRC GPC
to enable vertical free run mode set vfrc to 1 and dflw to 0 13 standard recognition status (see also: `automatic standard recognition') bit[0] bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] bit[7] bit[8] bit[9] bit[11:10] 14 CB 15 74 36 F0 input noise level number of lines per field, P/S: 312, N: 262 vertical field counter, incremented per field measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC) measured burst amplitude firmware version number bit[7:0] bit[11:8] 170 internal revision number firmware release read only MCV_STATUS read only read only read only 1 1 1 1 1 1 1 1 1 vertical lock horizontally locked no signal detected color amplitude killer active disable amplitude killer color ident killer active disable ident killer interlace detected no vertical sync detection spurious vertical sync detection reserved read only read only NOISE NLPF VCNT SAMPL BAMPL SW_VERSION - ASR
status of macrovision detection bit[0] bit[1] AGC pulse detected pseudo sync detected
46
Micronas
ADVANCE INFORMATION
VDP 313xY
Table 2-6: Control Registers of the Fast Processor for control of the video frontend functions -default values are initializied at reset
FP Subaddress
(hex)
Function
Default
(hex)
Name
171 172
bit[11:0] bit[11:0]
first line of macrovision detection window (relative to vsync) last line of macrovision detection window (relative to vsync)
6 15
MCV_START MCV_STOP
Scaler Control Register 40 scaler mode register bit[1:0] scaler mode 0 linear scaling mode 1 nonlinear scaling mode, 'panorama' 2 nonlinear scaling mode, 'waterglass' 3 reserved reserved, set to 0 scaler update 0 start scaler update command, when the registers are updated the bit is set to 1 57 57 4 SCUP 0 SCMODE MODE
bit[10:2] bit[11]
41
luma offset register bit[6:0] luma offset 0..127 ITU-R output format: CVBS output format:
YOFFS
this register is updated when the scaler mode register is written 42 active video length for 1-h FIFO bit[11:0] length in pixels 1080 FFLIM
this register is updated when the scaler mode register is written 43 scaler1 coefficient, this scaler is compressing the signal. For compression by a factor c the value c*1024 is required. bit[11:0] allowed values from 1024..4095 1024 SCINC1
this register is updated when the scaler mode register is written 44 scaler2 coefficient, this scaler is expanding the signal. For expansion by a factor c the value 1/c*1024 is required. bit[11:0] allowed values from 256..1024 1024 SCINC2
this register is updated when the scaler mode register is written 45 47 4B scaler1/2 nonlinear scaling coefficient this register is updated when the scaler mode register is written scaler1 window controls, see table 5 12-bit registers for control of the nonlinear scaling this register is updated when the scaler mode register is written 0 0 SCINC SCW1_0 - 4
Micronas
47
VDP 313xY
ADVANCE INFORMATION
Table 2-6: Control Registers of the Fast Processor for control of the video frontend functions -default values are initializied at reset
FP Subaddress
(hex)
Function
Default
(hex)
Name
4C 50
scaler2 window controls see table 5 12-bit registers for control of the nonlinear scaling this register is updated when the scaler mode register is written
0
SCW2_0 - 4
2.14.2.1. Scaler Adjustment In case of linear scaling, most of the scaler registers need not be set. Only the scaler mode, active video length, and the fixed scaler increments (scinc1/scinc2) must be written. The adjustment of the scaler for nonlinear scaling modes should use the parameters given in Table 2-7.
Table 2-7: Set-up values for nonlinear scaler modes Register Scaler Modes `waterglass' border 35% `panorama' border 30%
center compression 3/4 scinc1 scinc2 scinc fflim scw1 - 0 scw1 - 1 scw1 - 2 scw1 - 3 scw1 - 4 scw2 - 0 scw2 - 1 scw2 - 2 scw2 - 3 scw2 - 4 1643 1024 90 945 110 156 317 363 473 110 156 384 430 540 5/6 1427 1024 56 985 115 166 327 378 493 115 166 374 425 540 4/3 1024 376 85 921 83 147 314 378 461 122 186 354 418 540 6/5 1024 611 56 983 94 153 339 398 492 118 177 363 422 540
48
Micronas
ADVANCE INFORMATION
VDP 313xY
Table 2-8: Control Registers of the Fast Processor for control of the video backend functions-default values are initializied at reset FP Subaddress
(hex)
Function
Default
(hex)
Name
FP Display Control Register 130 131 132 139 13C White Drive Red (0...1023) White Drive Green (0...1023) White Drive Blue (0...1023) Internal Brightness, Picture (0...511), the center value is 256, the range allows for both increase and reduction of brightness. Internal Brightness, Measurement (0...511), the center value is 256, the brightness for measurement can be set to measure at higher cutoff current. The measurement brightness is independent of the drive values. Analog Brightness for external RGB (0...511), the center value is 256, the range allows for both increase and reduction of brightness. Analog Contrast for external RGB (0...511) 700 700 700 256 256 WDR 1) WDG 1) WDB 1) IBR IBRM
13A
256
ABR
13B
1)
350
ACT
The white drive values will become active only after writing the blue value WDB, latching of new values is indicated by setting the MSB of WDB.
FP Display Control Register, BCL 144 142 143 145 105 BCL threshold current, 0...2047 (max ADC output ~1152) BCL time constant 0...15 13 ... 1700 ms BCL loop gain. 0..15 BCL minimum contrast 0...1023 Test register for BCL/EHT comp. function, register value: 0 normal operation 1 stop ADC offset compensation x>1 use x in place of input from Measurement ADC Current BCL reduction (0...1023; read only) 1000 15 0 307 0 BCLTHR BCLTM BCLG BCLMIN BCLTST
60
1023
BCLREDUC
FP Display Control Register, Deflection 103 102 interlace offset, -2048..2047 This value is added to the SAWTOOTH output during one field. discharge sample count for deflection retrace, SAWTOOTH DAC output impedance is reduced for DSCC lines after vertical retrace. vertical discharge value, SAWTOOTH output value during discharge operation, typically same as A0 init value for sawtooth. EHT compensation vertical gain coefficient, 0...511 0 7 INTLC DSCC
11F
-1365
DSCV
10B
0
EHTV
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VDP 313xY
ADVANCE INFORMATION
Table 2-8: Control Registers of the Fast Processor for control of the video backend functions-default values are initializied at reset FP Subaddress
(hex)
Function
Default
(hex)
Name
10A 10F
EHT compensation time constant, 0...15 3.2..410 ms EHT compensation east/west gain coefficient, -512...511
15 0
EHTTM EHTEW
FP Display Control Register, Vertical Sawtooth 110 11B 11C 11D 11E DC offset of SAWTOOTH output This offset is independent of EHT compensation. accu0 init value accu1 init value accu2 init value accu3 init value 0 -1365 900 0 0 OFS A0 A1 A2 A3
FP Display Control Register, East-West Parabola 12B 12C 12D 12E 12F accu0 init value accu1 init value accu2 init value accu3 init value accu4 init value -1121 219 479 -1416 1052 A0 A1 A2 A3 A4
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ADVANCE INFORMATION
VDP 313xY
The initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for East-West deflection are 12-bit values. The coefficients that should be used to calculate the initialization values for different field frequencies are given below, the values must be scaled by 128, i.e. the value for a0 of the 50 Hz vertical deflection is:
a0 = (a * 128 - b * 1365.3 + c * 682.7 - d * 682.7) / 128
2.14.2.2. Calculation of Vertical and East-West Deflection Coefficients In Table 2-9 and Table 2-10 the formula for the calculation of the deflection initialization parameters from the polynominal coefficients a,b,c,d,e is given for the vertical and East-West deflection. Let the polynomial be
P : a + b(x - 0.5) + c(x - 0.5)2 + d(x - 0.5)3 + e(x - 0.5)4
Table 2-9: Calculation of Initialization values for Vertical Sawtooth Vertical Deflection 50 Hz a a0 a1 a2 a3 Vertical Deflection 60 Hz a a0 a1 a2 a3 128 b -1365.3 1083.5 c 682.7 -1090.2 429.9 d -682.7 1645.5 -1305.8 1023.5 128 b -1365.3 899.6 c 682.7 -904.3 296.4 d -682.7 1363.4 -898.4 585.9
Table 2-10: Calculation of Initialization values for East-West Parabola East-West Deflection 50 Hz a a0 a1 a2 a3 a4 East-West Deflection 60 Hz a a0 a1 a2 a3 a4 128 b -341.3 134.6 c 1365.3 -1083.5 849.3 d -85.3 102.2 -161.2 125.6 e 341.3 -548.4 1305.5 -2046.6 1584.8 128 b -341.3 111.9 c 1365.3 -899.6 586.8 d -85.3 84.8 -111.1 72.1 e 341.3 -454.5 898.3 -1171.7 756.5
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3. Specifications 3.1. Outline Dimensions
ADVANCE INFORMATION
SPGS703000-1(P64)/1E
64
33
1
32
57.7 0.1
0.8 0.2 3.8 0.1
19.3 0.1 18 0.05
0.28 0.06 3.2 0.2 1 0.05 1.778 0.48 0.06 31 x 1.778 = 55.1 0.1 20.3 0.5
Fig. 3-1: 64-Pin Plastic Shrink Dual-Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm
3.2. Pin Connections and Short Descriptions NC = not connected LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram Pin No.
PSDIP 64-pin
IN = Input OUT = Output SUPPLY = Supply Pin Short Description
Pin Name
Type
Connection
(If not used)
1 2 3 4 5 6 7 8 9 10 11
TEST RESQ SCL SDA GNDD HCS FSY CSY VS INTLC VPROT
IN IN IN/OUT IN/OUT SUPPLY IN OUT OUT OUT OUT IN
GNDD X X X X LV LV LV LV LV GNDAB
Test Input Reset Input I2C Bus Clock I2C Bus Data Digital Ground Half Contrast Switch Input Front Sync Output Composite Sync Output Vertical Sync Output (= VS Bit of MSY for TPU) Interlace Control Output Vertical Protection Input
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VDP 313xY
Pin No.
PSDIP 64-pin
Pin Name
Type
Connection
(If not used)
Short Description
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
SAFETY HFLB GNDD VSUPD GNDD VSUPD P0 P1 P2 P3 P4 P5 P6 GNDD RSW2 RSW1 SENSE GNDM VERTQ VERT E/W XREF SVMOUT GNDAB VSUPAB ROUT GOUT BOUT VRD RIN GIN
IN IN SUPPLY SUPPLY SUPPLY SUPPLY IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT SUPPLY OUT OUT IN SUPPLY OUT OUT OUT IN OUT SUPPLY SUPPLY OUT OUT OUT IN IN IN
GNDAB HOUT X X X LV LV LV GNDD GNDD GNDD GNDD GNDD X GNDAB GNDAB GNDAB X LV LV LV X VSUPAB X X VSUPAB VSUPAB VSUPAB X GNDAB GNDAB
Safety Input Horizontal Flyback Input Digital Ground Digital Supply Voltage (3.3 V) Digital Ground Digital Supply Voltage (3.3 V) Port 1, Bit 0 Port 1, Bit 1 Port 1, Bit 2 Port 1, Bit 3 Port 1, Bit 4 Port 1, Bit 5 Port 1, Bit 6 Digital Ground Range Switch 2 for Measurement ADC Range Switch 1 for Measurement ADC Sense ADC Input Ground, MADC Input Inverted Vertical Sawtooth Output Vertical Sawtooth Output Vertical Parabola Output Reference Input for RGB DACs Analog Scan Velocity Modulation Output Analog Ground Backend Analog Supply Voltage (5.0 V) Backend Analog Red Output Analog Green Output Analog Blue Output DAC Reference Analog Red Input Analog Green Input
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ADVANCE INFORMATION
Pin No.
PSDIP 64-pin
Pin Name
Type
Connection
(If not used)
Short Description
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
BIN FBLIN RIN2 GIN2 BIN2 FBLIN2 CLK20 HOUT XTAL 1 XTAL 2 CIN 2/CRIN CBIN GNDAF SGND VRT VSUPAF VOUT CIN1 VIN1 VIN2 VIN3 VIN4
IN IN IN IN IN IN OUT OUT IN OUT IN IN SUPPLY IN IN SUPPLY OUT IN IN IN IN IN
GNDAB GNDAB GNDAB GNDAB GNDAB GNDAB LV X X X LV LV X GNDAF X X LV VRT VRT VRT VRT VRT
Analog Blue Input Fast Blank Input Analog Red Input2 Analog Green Input2 Analog Blue Input2 Fast Blank Input2 20.25 MHz System Clock Output Horizontal Drive Output Analog Crystal Input Analog Crystal Output Analog Chroma 2/Component CR Input Component CB Input Analog Ground Frontend Signal Ground for Analog Input Reference Voltage Top, Video ADC Analog Supply Voltage (5.0 V) Frontend Analog Video Output Analog Chroma 1 Input Analog Video 1 Input Analog Video 2 Input Analog Video 3 Input Analog Video 4 Input
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ADVANCE INFORMATION
VDP 313xY
Pin 18-24 - IO Port Expander, PORT[6:0] (Fig. 3-21, Fig. 3-22) These pins provide an I2C programmable I/O port, which can be used to read and write slow external signals. Pin 25 - Ground (Digital Shield), GNDD. Pin 26, 27 - Range Switch for Measurement ADC, RSW1, RSW2 (Fig. 3-18) These pins are open drain pull-down outputs. RSW1 is switched off during cutoff and whitedrive measurement. RSW2 is switched off during cutoff measurement only. Pin 28 - Measurement ADC Input, SENSE (Fig. 3-19) This is the input of the analog digital converter for the picture and tube measurement. Pin 29 - Ground (Measurement ADC Reference Input), GNDM This is the ground reference for the measurement A/D converter. Pin 30 - Vertical Sawtooth Output Q, VERTQ (Fig. 3-16) This pin supplies the drive signal for the vertical output stage. The drive signal is generated with 15-bit precision by the Fast Processor in the front-end. The analog voltage is generated by a 4-bit current-DAC with external registor and uses digital noise shaping. Pin 31 - Vertical Sawtooth Output, VERT (Fig. 3-16) This pin supplies the inverted signal of pin 30. Together with pin 30 it can be used to drive symmetrical deflection amplifiers. Pin 32 - East-West Parabola Output, EW (Fig. 3-17) This pin supplies the parabola signal for the East-West correction. The drive signal is generated with 15 bit precision by the Fast Processor in the front-end. The analog voltage is generated by a 4-bit current-DAC with external resistor and uses digital noise shaping. Pin 33 - DAC Current Reference, XREF (Fig. 3-20) External reference resistor for DAC output currents, typical 10 k to adjust the output current of the D/A converters. (see recommended operating conditions). This resistor has to be connected to analog ground as closely as possible to the pin without any capacitor. Pin 34 - Scan Velocity Modulation Output, SVMOUT (Fig. 3-12) This output delivers the analog SVM signal. The D/A converter is a current sink like the RGB D/A converters. At zero signal the output current is 50 % of the maximum output current. Pin 35 - Ground (Analog Back-end), GNDAB Pin 36 - Supply Voltage (Analog Back-end), VSUPAB
3.3. Pin Descriptions Pin 1 - Test Input, TEST (Fig. 3-3) This pin enables factory test modes. For normal operation it must be connected to ground. Pin 2 - Reset Input, RESQ (Fig. 3-4) A low level on this pin resets the VDP31xxY. Pin 3 - I2C Bus Clock, SCL (Fig. 3-4) This pin connects to the I2C bus clock line. Pin 4 - I2C Bus Data, SDA (Fig. 3-4) This pin connects to the I2C bus data line. Pin 5 - Ground (Digital Shield), GNDD Pin 6 - Half Contrast Switch Input, HCS (Fig. 3-22) Via this input pin the output level of the analog RGB output pins can be reduced by 6 dB. Pin 7 - Front Sync Output, FSY (Fig. 3-21) This pin supplies the front sync information Pin 8 - Composite Sync Output, CSY (Fig. 3-21) This output supplies a standard composite sync signal that is compatible to the analog RGB output signals. Pin 9 - Vertical Sync Output, VS (Fig. 3-21) This pin supplies the vertical sync information. Pin 10 - Interlace Output, INTLC (Fig. 3-21) This pin supplies the interlace information, with programmable polarity. Pin 11 - Vertical Protection Input, VPROT (Fig. 3-14) The vertical protection circuitry prevents the picture tube from burn-in in the event of a malfunction of the vertical deflection stage. During vertical blanking, a signal level of 2.5 V is sensed. If a negative edge cannot be detected, the RGB output signals are blanked. Pin 12 - Safety Input, SAFETY (Fig. 3-14) This is a three-level input. Low level means normal function. At the medium level RGB signals are blanked and at high level RGB signals are blanked and horizontal drive is shut off. Pin 13 - Horizontal Flyback Input, HFLB (Fig. 3-14) Via this pin the horizontal flyback pulse is supplied to the VDP 313xY. Pin 14 - Ground (Digital Circuitry Front-end), GNDD Pin 15, 17- Supply Voltage (Digital Circuitry), VSUPD Pin 16 - Ground (Digital Circuitry Back-end), GNDD
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Pin 37, 38, 39 - Analog RGB Outputs, ROUT, GOUT, BOUT (Fig. 3-12) This are the analog Red/Green/Blue outputs of the backend. The outputs sink a current of max. 8 mA. Pin 40 - DAC Reference Decoupling, VRD (Fig. 3-20) Via this pin the DAC reference voltage is decoupled by an external capacitance. The DAC output currents depend on this voltage, therefore a pull-down transistor can be used to shut off all beam currents. A decoupling capacitor of 3.3 F/100 nF is required. Pin 41, 42, 43, 45, 46, 47 - Analog RGB Inputs, RIN1/ 2, GIN1/2, BIN1/2 (Fig. 3-11) These pins are used to insert an external analog RGB signal, e.g. from a SCART connector which can by switched to the analog RGB outputs with the fast blank signal. The analog backend provides separate brightness and contrast settings for the external analog RGB signals. Pin 44, 48 - Fast Blank Inputs, FBLIN1/2 (Fig. 3-15) These pins are used to switch the RGB outputs to the external analog RGB inputs. Pin 49 - Main Clock Output, CLK20 ( Fig. 3-6) This is the 20.25 MHz main system clock, that is used by all circuits in a high-end VDP system. All external timing is derived from this clock. Pin 50 - Horizontal Drive Output, HOUT (Fig. 3-13) This open drain output supplies the the drive pulse for the horizontal output stage. The polarity and gating with the flyback pulse are selectable by software. Pin 51, 52 - Crystal Input and Output, XTAL1, XTAL2 (Fig. 3-5) These pins are connected to an 20.25 MHz crystal oscillator is digitally tuned by integrated shunt capacitances. The Clk20 signal is derived from this oscillator. Pin 53, 54, 60- Analog Chroma Inputs, CIN1, CIN2/ CRIN, CBIN, (Fig. 3-7, Fig. 3-8) CIN1, CIN2 are the analog chroma inputs for S-VHS. A S-VHS chroma signal is converted using the chroma (Video2) AD converter. A resistive devider is used to BIAS the inout signal to middle of converter range. The input signal must be AC coupled. Together with the CBIN pin CIN2 can alternatively be used as chroma component input for the analog YCRCB interface. Pin 55 - Ground (Analog Front-end), GNDAF Pin 56 - Ground (Analog Signal Input), SGND (Fig. 3-10) This is the high quality ground reference for the video input signals.
ADVANCE INFORMATION
Pin 57 - Reference Voltage Top, VRT (Fig. 3-10) Via this pin, the reference voltage for the A/D converters is decoupled. The pin is connected with 10 F/ 47 nF to the Signal Ground Pin. Pin 58 - Supply Voltage (Analog Front-end), VSUPAF Pin 59 - Analog Video Output, VOUT (Fig. 3-9) The analog video signal that is selected for the main (luma, cvbs) adc is output at this pin. An emitter follower is required at this pin. Pin 61...64 - Analog Video Input 1-4, VIN1-4 (Fig. 3- 7) These are the analog video inputs. A CVBS or S-VHS luma signal is converted using the luma (Video 1) AD converter. The input signal must be AC-coupled.
3.4. Pin Configuration
TEST 1
RESQ SCL SDA GNDD HCS FSY CSY VS INTLC VPROT SAFETY HFLB GNDD VSUPD GNDD VSUPD P0 P1 P2 P3 P4 P5 P6 GNDD RSW2 RSW1 SENSE GNDM VERTQ VERT E/W 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VIN4 VIN3 VIN2 VIN1 CIN1 VOUT VSUPAF VRT SGND GNDAF CBIN CIN 2/CRIN XTAL 2 XTAL 1 HOUT CLK20 FBLIN2 BIN2 GIN2 RIN2 FBLIN BIN GIN RIN VRD BOUT GOUT ROUT VSUPAB GNDAB SVMOUT XREF
Fig. 3-2: 64-pin PSDIP package
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VDP 313xY
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ADVANCE INFORMATION
VDP 313xY
3.5. Pin Circuits VSUPAF VSUPD To ADC GNDAF Fig. 3-8: Input pins CIN1,CIN2
GNDD Fig. 3-3: Input pin TEST, RESQ
VSUPAF VINx N GNDD Fig. 3-4: Input/Output pins SDA, SCL VREF N GNDAF Fig. 3-9: Output pin VOUT P XTAL2
0.5 M
- +
P
P P
VSUPD - + = VREF VSUPAF P VRT ADC Reference SGND Fig. 3-10: Supply pins VRT, SGND
fXTAL N N N GNDD
XTAL1
Fig. 3-5: Input/Output pins XTAL1, XTAL2
VSUPD P P Clamping N
N
GNDAB N N GNDD Fig. 3-6: Output pin CLK20 N VSUPAF Bias N GNDAB To ADC Fig. 3-12: Output pins ROUT, GOUT, BOUT, SVMOUT Fig. 3-11: Input pins RIN, GIN, BIN
GNDAF Fig. 3-7: Input pins VIN1-VIN4, CBIN, CRIN
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ADVANCE INFORMATION
N GNDD Fig. 3-13: Output pin HOUT
N GNDAB Fig. 3-18: Output pins RSW1, RSW2
P VREF Fig. 3-14: Input pins SAFETY, HFLB, VPROT Fig. 3-19: Input pin SENSE N
VSUPAB VREF Fig. 3-15: Input pins FBLIN VRD int. ref. voltage VSUPAB P P P VERTQ VERT P N GNDAB N Fig. 3-16: Output pins VERT, VERTQ GNDD Fig. 3-21: Output pins FSY, VS, CSY, INTLC, PORT[6:0] VSUPD
Flyback
+ -
ref. current XREF GNDAB
Fig. 3-20: Supply pins XREF, VRD
VSUPAB
P
P
VSUPD
VEWXR
N GNDAB
GNDD Fig. 3-22: Input pins HCS, PORT[6:0]
Fig. 3-17: Output pin EW
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VDP 313xY
3.6. Electrical Characteristics 3.6.1. Absolute Maximum Ratings Symbol TJ TS PTOT VSUPx VI VO VIO VES
1) Refer 2)
Parameter Junction Temperature Storage Temperature Total Power Dissipation Supply Voltage Input Voltage, all Inputs Output Voltage, all Outputs Input/Output Voltage, all Open Drain Outputs Electrostatic Handling, HBM 2)
Pin Name
Min. 0 -40 -
Max. 125 125 1400 6 VSUPx+0.31) VSUPx+0.31) 6 +2000
Unit C C mW V V V V V
VSUPx
-0.3 -0.3 -0.3 -0.3 -2000
to Pin Circuits (chapter 3.5. on page 57) Human Body Model (HBM): R=1.5 k, C=100 pF ing Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operat-
3.6.2. Recommended Operating Conditions Symbol TA fXTAL VSUPA VSUPD Parameter Ambient Operating Temperature Clock Frequency Analog Supply Voltage Digital Supply Voltage XTAL1/2 VSUPAF VSUPAB VSUPD Pin Name Min. 0 - 4.75 3.15 Typ. - 20.25 5.0 3.3 Max. 65 - 5.25 3.45 Unit C MHz V V
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3.6.2.1. Analog Input and Output Recommendations Symbol Video VVIN VCIN CVIN CCIN CCCIN RGB Rxref CRGBIN RGB-DAC Current defining Resistor RGB Input Coupling Capacitor XREF RIN GIN BIN 9.5 - 10 15 Video Input Level Chroma Input Level Input Coupling Capacitor Video Inputs Input Coupling Capacitor Chroma Inputs Input Coupling Capacitor Component Inputs VIN1-4, CIN1-2 CRIN, CBIN VIN1-4 CIN1-2 CRIN, CBIN 0.5 - - - - 1.0 700 680 1 220 Parameter Pin Name Min.
ADVANCE INFORMATION
Typ.
Max.
Unit
3.5 - - - -
VPP mV nF nF nF
10.5 -
k nF
Deflection Rload Cload Deflection Load Resistance Deflection Load Capacitance EW, VERT, VERTQ - - 6.8 68 - - k nF
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VDP 313xY
3.6.3. Recommended Crystal Characteristics Symbol TA fP fP/fP fP/fP RR C0 C1 Parameter Operating Ambient Temperature Parallel Resonance Frequency with Load Capacitance CL = 13 pF Accuracy of Adjustment Frequency Temperature Drift Series Resistance Shunt Capacitance Motional Capacitance Min. 0 - - - - 3 20 Typ. - 20.250000 - - - - - Max. 65 - 20 30 25 7 30 Unit C MHz ppm ppm pF fF
Load Capacitance Recommendation CLext External Load Capacitance 1) from pins to Ground (pin names: Xtal1 Xtal2) - 3.3 - pF
DCO Characteristics 2,3) CICLoadmin Effective Load Capacitance @ min. DCO-Position, Code 0, package: 64PSDIP Effective Load Capacitance Range, DCO Codes from 0..255 3 4.3 5.5 pF
CICLoadrng
1) Remarks
11
12.7
15
pF
on defining the External Load Capacitance: External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load capacitance of the PCBs to the required load capacitance CL of the crystal. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match fp MHz. Due to different layouts of customer PCBs the matching capacitor size should be determined in the application. The suggested value is a figure based on experience with various PCB layouts. Tuning condition: Code DVCO Register = -720 2) Remarks on Pulling Range of DCO: The pulling range of the DCO is a function of the used crystal and effective load capacitance of the IC (CICLoad +CLoadBoard). The resulting frequency fL with an effective load capacitance of CLeff = CICLoad + CLoadBoard is: 1 + 0.5 x [ C1 / (C0 + CLeff) ] fL = fP x _______________________ 1 + 0.5 x [ C1 / (C0 + CL) ]
3)
Remarks on DCO codes The DCO hardware register has 8 bits, the fp control register uses a range of -2048...2047
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3.6.4. Characteristics
ADVANCE INFORMATION
If not otherwise designated under test conditions, all characteristics are specified for recommended operating conditions (see Section 3.6.2. on page 59).
3.6.4.1. General Characteristics
Symbol PTOT IVSUPD IVSUPAF IVSUPAB IL Parameter Total Power Dissipation Current Consumption Digital Circuitry Current Consumption Analog Frontend Current Consumption Analog Backend Input and Output Leakage Current VSUPD VSUPAF VSUPAB All I/O Pins Pin Name Min. - - - - -1 Typ. 900 118 35 58 - Max. 1400 - - - 1 Unit mW mA mA mA A depends on contrast and brightness settings Test Conditions
3.6.4.2. I2C Bus Interface
Symbol VIL VIH VOL VIH tF tR fSCL tLOW tHIGH tSU Data tHD Data Parameter Input Low Voltage Input High Voltage Output Low Voltage Input Capacitance Signal Fall Time Signal Rise Time Clock Frequency Low Period of SCL High Period of SCL Data Set Up Time to SCL high DATA Hold Time to SCL low SDA SCL Pin Name SDA, SCL Min. - 0.6 - - - - 0 1.3 0.6 100 0 Typ. - - - - - - - - - - - Max. 0.3 - 0.4 0.6 5 300 300 400 - - - 0.9 Unit VSUPD VSUPD V V pF ns ns kHz s s ns s CL = 400 pF CL = 400 pF Il = 3 mA Il = 6 mA Test Conditions
3.6.4.3. Reset Input
Symbol VIL VIH Parameter Input Low Voltage Input High Voltage Pin Name RESQ RESQ Min. - 2 Typ. - - Max. 0.8 - Unit V V Test Conditions
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3.6.4.4. Power-up Sequence
Symbol tVdel tVrmpl Parameter Ramp Up Difference of Supplies Transition Time of Supplies Pin Name Min. 0 - Typ. - - Max. 1 50 Unit s ms Test Conditions
tVrmp 0.9 x VSUPAI VSUPF
tVdel
time / ms
0.9 x VSUPD VSTBY
time / ms max. 1 ms (maximum guaranteed start-up time) LLC
time / ms RESQ 0.8 x VSUPD min. 1 s
max. 0.05 ms SDA/SCL
time / ms
I2C-cycles invalid
time / ms Fig. 3-23: Power-Up sequence
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3.6.4.5. Test Input
Symbol VIL VIH Ipd Parameter Input Low Voltage Input High Voltage Input Pull-Down Current Pin Name TEST Min. - 2.0 25 Typ. - - 80 Max. 0.8 - 170 Unit V V A
ADVANCE INFORMATION
Test Conditions
Vi = VSUPD
3.6.4.6. Analog Video Front-End and A/D Converters
Symbol VVRT VVRTN Luma - Path RVIN CVIN VVIN VVIN AGC DNLAGC Input Resistance Input Capacitance Full Scale Input Voltage Full Scale Input Voltage AGC step width AGC Differential Non-Linearity Input Clamping Level, CVBS Clamping DAC Resolution Input Clamping Current per step Clamping DAC Differential Non-Linearity VIN1-4 1 - 1.8 0.5 - - - 5 2.0 0.6 0.166 - - - 2.2 0.7 - 0.5 M pF VPP VPP dB LSB min. AGC Gain max. AGC Gain 6-Bit Resolution= 64 Steps fsig= 1 MHz, - 2 dBr of max. AGC- Gain Binary Level = 64 LSB min. AGC Gain 5 Bit - I-DAC, bipolar VVIN=1.5 V Code Clamp-DAC=0 Parameter Reference Voltage Top Reference Voltage Top Noise Pin Name VRT Min. 2.5 - Typ. 2.6 - Max. 2.8 100 Unit V mVPP Test Conditions 10 F/10 nF, 1 G Probe
VVINCL QCL ICL-LSB DNLICL
- -16 0.7 -
1.0 - 1.0 -
- 15 1.3 0.5
V steps mA LSB
Chroma - Path (composite) RCIN VCIN VCINDC Input Resistance SVHS Chroma Full Scale Input Voltage, Chroma Input Bias Level, SVHS Chroma Binary Code for Open Chroma Input Chroma - Path (component) RVIN CVIN VVIN VVIN Input Resistance Input Capacitance Full Scale Input Voltage Full Scale Input Voltage 0.76 1.08 0.84 1.2 CBIN, CRIN 1 4.5 0.92 1.32 M pF VPP VPP minimal range extended range Code Clamp-DAC = 0 CIN1 CIN2 1.4 1.08 - - 2.0 1.2 1.5 128 2.6 1.32 - - k VPP V -
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VDP 313xY
Symbol VINCL QCL ICL-LSB DNLICL
Parameter Input Clamping Level CR, CB Clamping DAC Resolution Input Clamping Current per step Clamping DAC Differential Non-Linearity
Pin Name
Min.
Typ. 1.5
Max.
Unit V
Test Conditions Binary Level = 128 LSB 6 Bit - I-DAC, bipolar VVIN = 1.5 V
-32 0.59 0.85
31 1.11 0.5
steps A LSB
Dynamic Characteristics for all Video-Paths (Luma + Chroma) BW XTALK THD SINAD INL DNL DG DP Bandwidth Crosstalk, any Two Video Inputs Total Harmonic Distortion Signal to Noise and Distortion Ratio Integral Non-Linearity Differential Non-Linearity Differential Gain Differential Phase VIN1-4 CIN1-2 CBIN 8 - - - - - - - 10 -56 50 45 - - - - - - - - 1 0.8 3 1.5 MHz dB dB dB LSB LSB % deg -12 dBr, 4.4 MHz signal on DC-ramp -2 dBr input signal level 1 MHz, -2 dBr signal level 1 MHz, 5 harmonics, -2 dBr signal level 1 MHz, all outputs, -2 dBr signal level Code Density, DC-ramp
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3.6.4.7. Horizontal Flyback Input
Symbol VIL VIH VIHST PSRRHF PSRRMF PSRRLF Parameter Input Low Voltage Input High Voltage Input Hysteresis Power Supply Rejection Ratio of Trigger Level Power Supply Rejection Ratio of Trigger Level Power Supply Rejection Ratio of Trigger Level Pin Name HFLB Min. - 2.6 0.1 0 -20 -40 Typ. - - - - - - Max. 1.8 - - - - - Unit V V V dB dB dB
ADVANCE INFORMATION
Test Conditions
f = 20 MHz f < 15 kHz f < 100 Hz
3.6.4.8. Horizontal Drive Output
Symbol VOL VOH tOF IOL Parameter Output Low Voltage Output High Voltage (Open Drain Stage) Output Fall Time Output Low Current Pin Name HOUT Min. - - - - Typ. - - 8 - Max. 0.4 5 20 10 Unit V V ns mA Test Conditions IOL = 10 mA external pull-up resistor CLOAD = 30 pF
3.6.4.9. Vertical Protection Input
Symbol VIL VIH VIHST Parameter Input Low Voltage Input High Voltage Input Hysteresis Pin Name VPROT Min. - 2.6 0.1 Typ. - - - Max. 1.8 - - Unit V V V Test Conditions
3.6.4.10. Vertical Safety Input
Symbol VILA VIHA VILB VIHB VIHST tPID Parameter Input Low Voltage A Input High Voltage A Input Low Voltage B Input High Voltage B Input Hysteresis A and B Internal Delay Pin Name SAFETY Min. - 2.6 - 3.8 0.1 - Typ. - - - - - - Max. 1.8 - 3.0 - - 100 Unit V V V V V ns Test Conditions
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ADVANCE INFORMATION
VDP 313xY
3.6.4.11. Vertical and East/West D/A Converter Output
Symbol VOMIN VOMAX IDACN PSRR Parameter Minimum Output Voltage Maximum Output Voltage Full scale DAC Output Current Power Supply Rejection Ratio Pin Name EW VERT VERTQ Min. - 2.82 415 - Typ. 0 3 440 20 Max. - 3.2 465 - Unit V V A dB Test Conditions Rload = 6.8 k Rxref = 10 k Rload = 6.8 k Rxref = 10 k Rxref = 10 k
3.6.4.12. Combined Sync, Vertical Sync, Interlace and Front Sync Output
Symbol VOL VOH Parameter Output Low Voltage Output High Voltage Pin Name CSY VS INTLC FSY Min. - VSUPD - 0.4 Typ. 0.2 - Max. 0.4 VSUPD Unit V V Test Conditions IOL = 1.6 mA -IOL = 1.6 mA
3.6.4.13. CLK20 Output
Symbol VOL VOH Parameter Output Low Voltage Output High Voltage Pin Name CLK20 Min. - VSUPD - 0.4 Typ. 0.2 - Max. 0.4 VSUPD Unit V V Test Conditions IOL = TBD; strenght = TBD IOL = TBD; strenght = TBD
3.6.4.14. Sense A/D Converter Input
Symbol VI VI255 C0 RI Parameter Input Voltage Range Input Voltage for code 255 Digital Output for zero Input Input Impedance Pin Name SENSE Min. 0 1.4 - 1 Typ. - 1.54 - - Max.
VSUPAB
Unit V V LSB M
Test Conditions
1.7 16 -
Read cutoff blue register Offset check,read cutoff blue register
3.6.4.15. Range Switch Output
Symbol RON IMax ILEAK Parameter Output On Resistance Maximum Current Leakage Current Pin Name RSW1 RSW2 Min. - - - Typ. - - - Max. 50 15 600 Unit mA nA RSW High Impedance Test Conditions IOL = 10 mA
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VDP 313xY
3.6.4.16. Scan Velocity Modulation Output
Symbol Parameter Resolution IOUT IOUT IOUT IOUT Full Scale Output Current Differential Nonlinearity Integral Nonlinearity Glitch Pulse Charge Pin Name SVMOUT Min. - 1.55 - - - Typ. 8 1.875 - - 0.5 Max. - 2.25 0.5 1 - Unit bit mA LSB LSB pAs
ADVANCE INFORMATION
Test Conditions
Ramp, output line is terminated on both ends with 50 10 % to 90 %, 90 % to 10 %
IOUT
Rise and Fall Time
-
3
-
ns
3.6.4.17. D/A Converter Reference
Symbol VDACREF VDACR VXREF Parameter DAC-Ref. Voltage DAC-Ref. Output resistance DAC-Ref. Voltage Bias Current Generation XREF Pin Name VRD Min. 2.38 18 2.38 Typ. 2.50 25 2.5 Max. 2.63 32 2.63 Unit V k V Rxref = 10 k Test Conditions
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VDP 313xY
3.6.4.18. Analog RGB and FB Inputs
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
RGB Input Characteristics VRGBIN VRGBIN VRGBIN External RGB Inputs Voltage Range nominal RGB Input Voltage peak-to-peak RGB Inputs Voltage for Maximum Output Current RIN1/2 GIN1/2 BIN1/2 -0.3 0.5 - - - tCLP CIN IIL VCLIP VCLAMP VINOFF VINOFF RCLAMP Clamp Pulse Width Input Capacitance Input Leakage Current RGB Input Voltage for Clipping Current Clamp Level at Input Offset Level at Input Offset Level Match at Input Clamping-ON-Resistance 1.6 - -0.5 - 40 -10 -10 - - 0.7 0.44 0.7 1.1 - - - 2 60 - - 140 1.1 1.0 - - - - 13 0.5 - 80 10 10 - V VPP V V V s pF A V mV mV mV Clamping ON Extrapolated from VIN = 100 and 200 mV Extrapolated from VIN = 100 and 200 mV Clamping OFF, VIN = -0.3...3 V SCART Spec: 0.7 V 3 dB Contrast setting: 511 Contrast setting: 323 Contrast setting: 204
Fast Blank Input Characteristics VFBLOFF VFBLON VFBLTRIG tPID FBLIN Low Level FBLIN High Level Fast Blanking Trigger Level typical Delay Fast Blanking to RGBOUT from midst of FBLIN-transition to 90 % of RGBOUT- transition FBLIN1/2 - 0.9 - - - - 0.7 8 0.5 - - 15 V V V ns Internal RGB = 3.75 mA Full Scale Int. Brightness = 0 External Brightness = 1.5 mA (Full Scale) RGBin = 0 VFBLOFF = 0.4 V VFBLON = 1.0 V Rise and fall time = 2 ns
Difference of Internal Delay to External RGBin Delay Switch-Over-Glitch
-5 -
- 0.5
+5 -
ns pAs Switch from 3.75 mA (int) to 1.5 mA (ext)
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VDP 313xY
3.6.4.19. Half Contrast Switch Input
Symbol VIL VIH tHCS Parameter Input Low Voltage Input High Voltage Delay HCS to RGBOUT from 50 % of HCS-transition to 90 % of RGBOUT-transition Pin Name HCS Min. - 1.5 Typ. - - 80 Max. 0.8 - 120 Unit V V ns
ADVANCE INFORMATION
Test Conditions
Internal GRB = 3.75 mA VHCSL = 0.4 V VHCSH = 1.0 V Rise and fall time = 2 ns
3.6.4.20. Analog RGB Outputs, D/A Converters
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Internal RGB Signal D/A Converter Characteristics Resolution IOUT IOUT IOUT IOUT IOUT IOUT IOUT IOUT Full Scale Output Current Differential Nonlinearity Integral Nonlinearity Glitch Pulse Charge Rise and Fall Time Intermodulation Signal to Noise Matching R-G, R-B, G-B R/B/G Crosstalk one channel talks two channels talk RGB Input Crosstalk from external RGB one channel talks two channels talk three channels talk Internal RGB Brightness D/A Converter Characteristics Resolution IBR IBR IBR IBR IBR IBR Full Scale Output Current relative Full Scale Output Current absolute Differential Nonlinearity Integral Nonlinearity Match R-G, R-B, G-B Match to digital RGB R-R, G-G, B-B ROUT GOUT BOUT - 39.2 - - - -2 -2 9 40 1.5 - - - - - 40.8 - 1 2 2 2 bit % mA LSB LSB % % Ref to max. digital RGB ROUT GOUT BOUT - 3.6 - - - - - +50 -2 - 10 3.75 - - 0.5 3 - - - - - 3.9 0.5 1 - - -50 - 2 -46 bit mA LSB LSB pAs ns dB dB % dB Passive channel: IOUT =1.88 mA Crosstalk-Signal: 1.25 MHz, 3.75 mAPP Ramp signal, 25 output termination 10 % to 90 %, 90 % to 10 % 2/2.5 MHz full scale Signal: 1 MHz full scale Bandwidth: 10 MHz Rref = 10 k
- - -
- - -
-50 -50 -50
dB dB dB
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ADVANCE INFORMATION
VDP 313xY
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
External RGB Voltage/Current Converter Characteristics Resolution IEXOUT Full Scale Output Current relative Full Scale Output Current absolute CR Contrast Adjust Range Gain Match R-G, R-B, G-B ROUT GOUT BOUT - 96 9 100 - 104 bit % Ref. to max. Digital RGB VIN = 0.7 VPP, contrast = 323 Same as Digital RGB
- - -2
3.75 16:511 -
- - 2
mA
%
Measured at RGB Outputs VIN = 0.7 V, contrast = 323 Measured at RGB Outputs VIN = 0.7 V, contrast = 323 Passive channel: VIN = 0.7 V, contrast = 323 Crosstalk signal: 1.25 MHz, 3.75 mAPP
Gain Match to RGB-DACs R-R, G-G, B-B R/B/G Input Crosstalk one channel talks two channels talk RGB Input Crosstalk from Internal RGB one channel talks two channels talk tree channels talk RGB Input Noise and Distortion RGB Input Bandwidth -3dB RGB Input THD
-3
-
3
%
-
-
-46
dB
-
-
-50
dB
-
-
-50
dB
VIN=0.7 VPP at 1 MHz contrast = 323 Bandwidth: 10 MHz VIN = 0.7 VPP, contrast =323 Input signal 1 MHz Input signal 6 MHz VIN = 0.7 VPP contrast =323 VIN = 0.44 V
15 - - -50 -40
- - -
MHz dB dB
Differential Nonlinearity of Contrast Adjust Integral Nonlinearity of Contrast Adjust VRGBO R,G,B Output Voltage R,G,B Output Load Resistance VOUTC RGB Output Compliance
- - -1.0 - -1.5
- - - - -1.3
1 2 0.3 100 -1.2
LSB LSB V V
Referred to VSUPO Ref. to VSUPO Ref. to VSUPO Sum of max. Current of RGBDACs and max. Current of Int. Brightness DACs is 2 % degraded
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VDP 313xY
ADVANCE INFORMATION
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
External RGB Brightness D/A Converter Characteristics Resolution IEXBR Full Scale Output Current relative Full Scale Output Current absolute Differential Nonlinearity Integral Nonlinearity Matching R-G, R-B, G-B Matching to digital RGB R-R, G-G, B-B RGB Output Cutoff D/A Converter Characteristics Resolution ICUT Full Scale Output Current relative Full Scale Output Current absolute Differential nonlinearity Integral nonlinearity Matching to digital RGB R-R, G-G, B-B RGB Output Ultrablack D/A Converter Characteristics Resolution IUB Full Scale Output Current relative Full Scale Output Current absolute Match to digital RGB R-R, G-G, B-B ROUT GOUT BOUT - 19.6 - -2 1 20 0.75 - - 20.4 - 2 bit % mA % Ref to max. digital RGB ROUT GOUT BOUT - 58.8 - - - -2 9 60 2.25 - - - - 61.2 - 1 2 2 bit % mA LSB LSB % Ref to max. digital RGB ROUT GOUT BOUT - 39.2 - - - -2 -2 9 40 1.5 - - - - - 40.8 - 1 2 2 2 bit % mA LSB LSB % % Ref to max. digital RGB
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ADVANCE INFORMATION
VDP 313xY
3.6.4.21. IO Ports
Symbol Vol Voh Vol Voh VIL VIH Ii Parameter Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Leakage Current VSUPD -1 V - 2.0 -0.1 - - - 0.8 - 0.1 V V uA 0Micronas
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VDP 313xY
4. Application Circuit
ADVANCE INFORMATION
Fig. 4-1: VDP 313xY Application Circuit
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Micronas
ADVANCE INFORMATION
VDP 313xY
Micronas
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VDP 313xY
5. Data Sheet History 1. Advance Information: "VDP 313xY Video Processor Family", August 15, 2000, 6251-519-1AI. First release of the advance information.
ADVANCE INFORMATION
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-519-1AI
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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